| 1 | | Add support for LEON 2 and 3 CPUs (which are based on SPARC V8). |
| | 1 | Implement support for LEON2 and/or LEON3 CPUs (sparc32 big-endian architecture). |
| | 2 | |
| | 3 | Details:: |
| | 4 | The LEON CPU is a 32bit CPU microarchitecture based on the SPARCv8 RISC architecture and instruction set. It was designed by ESTEC (European Space Research and Technology Centre) which is part of ESA (European Space Agency) and later by Gaisler Research. The CPU is described in a synthesizable and configurable VHDL with generics, licensed under GPL/LGPL. Various variants of the LEON CPU are used for space on-board software and for ground development of such software (as fault-tolerant radiation hardened ASICs if used actually in space and usually as FPGAs for the development). |
| | 5 | |
| | 6 | There are several generations of the LEON CPU. LEON2 and LEON3 are the most frequently used. Each CPU design (IP core) is also accomplished by the infrastructure (support cores) with which the processor is packaged (e.g. an interrupt controller, memory controller, timers, UARTs, I/O ports, plug-and-play AMBA bus, etc.). |
| | 7 | |
| | 8 | The goal of this ticket is to pick a generic LEON distribution and port HelenOS to it. At least basic system functionality is required, i.e. support for booting, memory management, scheduling, user space, IPC and user input/output (via a serial console or similar). The microarchitecture and instruction set of LEON CPUs is reasonably similar to the 64bit SPARCv9 that is already supported by HelenOS. The main differences are: |
| | 9 | |
| | 10 | * 32 bits instead of 64 bits (registers, word size, etc.) |
| | 11 | * no trap nesting, trap inside trap would cause watchdog reset |
| | 12 | * on SPARCv9 non-register window traps will not do a SAVE while on SPARCv8 they will |
| | 13 | * registers controlling the register stack engine move in the opposite direction |
| | 14 | |
| | 15 | What Gains and Benefits will this bring?:: |
| | 16 | The LEON CPUs are used for space missions both by ESA and NASA, it is also an excellent example of a clean embedded SoC design (arguably better and more open than many ARM SoC designs). Thus implementing LEON support for HelenOS might make it a possible operating system of choice for some embedded applications. |
| | 17 | |
| | 18 | Difficulty:: |
| | 19 | High |
| | 20 | |
| | 21 | Required skills:: |
| | 22 | While the complete designs of LEON CPUs are readily available, there are many configuration options of the design and many ways how to deploy the design in physical hardware (i.e. on a FPGA). There are also several LEON emulators (TSIM, EGOS, etc.) with different feature sets. Therefore a successful applicant will need to have very good skills in programming in the C language and the ability to learn and reuse know-how contained in specifications, VHDL, reverse-engineered code of other operating system projects, etc. |
| | 23 | |
| | 24 | Note:: |
| | 25 | We have an FPGA board that is capable to host the LEON2 design. It is available for development, debugging and testing. |
| | 26 | |
| | 27 | Documentation:: |
| | 28 | |
| | 29 | * [http://en.wikipedia.org/wiki/LEON LEON] |
| | 30 | * [http://www.rte.se/blog/blogg-modesty-corex/leon3-soft-processor LEON3 tutorial] |
| | 31 | * [http://www.gaisler.com/ Gaisler Research] |
| | 32 | * [http://tldp.org/HOWTO/html_single/SPARC-HOWTO/#ss2.6 Linux SPARC HOWTO, Section LEON] |
| | 33 | |
| | 34 | Possible mentors:: |
| | 35 | HelenOS Core Team, Martin Decky |
