USB performance regression of mainline from the USB development branch
|Reported by:||Jakub Jermář||Owned by:|
|Blocker for:||Depends on:|
After having been merged to HelenOS in mainline,1006, the USB subsystem seems to have much larger latency than it had in the USB development branch.
The cause may be related to reversion of the change in cacheablitity of address space areas which was made as part of the mainline,1006:
sys_as_create_area() now creates cacheable areas by default
Note that this is no change against mainline, but a change against the USB development branch, where cacheability is not explicitly enforced on address space areas.
If this hypothesis is correct, we should cautiously merge even that aspect of the USB development branch. Caution is due as I remember some architectures (e.g. sparc64) are rather sensitive to changes in cacheability.