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00035 #ifndef __mips32_CP0_H__
00036 #define __mips32_CP0_H__
00037
00038 #include <arch/types.h>
00039 #include <arch/mm/tlb.h>
00040
00041 #define cp0_status_ie_enabled_bit (1<<0)
00042 #define cp0_status_exl_exception_bit (1<<1)
00043 #define cp0_status_erl_error_bit (1<<2)
00044 #define cp0_status_um_bit (1<<4)
00045 #define cp0_status_bev_bootstrap_bit (1<<22)
00046 #define cp0_status_fpu_bit (1<<29)
00047
00048 #define cp0_status_im_shift 8
00049 #define cp0_status_im_mask 0xff00
00050
00051 #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
00052 #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
00053
00054 #define fpu_cop_id 1
00055
00056
00057
00058
00059 #define cp0_compare_value 100000
00060
00061 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
00062 #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
00063 #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
00064 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
00065
00066 #define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
00067 { \
00068 __u32 retval; \
00069 asm("mfc0 %0, $" #reg : "=r"(retval)); \
00070 return retval; \
00071 }
00072
00073 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
00074 { \
00075 asm("mtc0 %0, $" #reg : : "r"(val) ); \
00076 }
00077
00078 GEN_READ_CP0(index, 0);
00079 GEN_WRITE_CP0(index, 0);
00080
00081 GEN_READ_CP0(random, 1);
00082
00083 GEN_READ_CP0(entry_lo0, 2);
00084 GEN_WRITE_CP0(entry_lo0, 2);
00085
00086 GEN_READ_CP0(entry_lo1, 3);
00087 GEN_WRITE_CP0(entry_lo1, 3);
00088
00089 GEN_READ_CP0(context, 4);
00090 GEN_WRITE_CP0(context, 4);
00091
00092 GEN_READ_CP0(pagemask, 5);
00093 GEN_WRITE_CP0(pagemask, 5);
00094
00095 GEN_READ_CP0(wired, 6);
00096 GEN_WRITE_CP0(wired, 6);
00097
00098 GEN_READ_CP0(badvaddr, 8);
00099
00100 GEN_READ_CP0(count, 9);
00101 GEN_WRITE_CP0(count, 9);
00102
00103 GEN_READ_CP0(entry_hi, 10);
00104 GEN_WRITE_CP0(entry_hi, 10);
00105
00106 GEN_READ_CP0(compare, 11);
00107 GEN_WRITE_CP0(compare, 11);
00108
00109 GEN_READ_CP0(status, 12);
00110 GEN_WRITE_CP0(status, 12);
00111
00112 GEN_READ_CP0(cause, 13);
00113 GEN_WRITE_CP0(cause, 13);
00114
00115 GEN_READ_CP0(epc, 14);
00116 GEN_WRITE_CP0(epc, 14);
00117
00118 GEN_READ_CP0(prid, 15);
00119
00120 #endif
00121