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Changeset mainline,1739


Ignore:
Timestamp:
2012-12-31T08:41:10Z (4 years ago)
Author:
Beniamino Galvani <b.galvani@…>
authors:
Beniamino Galvani <b.galvani@gmail.com>
branch-nick:
HelenOS.mainline
revision id:
jakub@jermar.eu-20121231084110-iakpoy3hl0etrh3g
Message:

Enable ARM caches in the boot stage of HelenOS to speed up the
decompression. We get a decompression time of 8 seconds on a mini2440
board and only slightly more on a GTA02.

Location:
mainline/boot/arch/arm32
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • mainline/boot/arch/arm32/include/mm.h

    r8.1.72 r1739  
    4747/** Describe "section" page table entry (one-level paging with 1 MB sized pages). */
    4848#define PTE_DESCRIPTOR_SECTION  0x02
     49/** Shift of memory address in section descriptor */
     50#define PTE_SECTION_SHIFT  20
    4951
    5052/** Page table access rights: user - no access, kernel - read/write. */
    5153#define PTE_AP_USER_NO_KERNEL_RW  0x01
     54
     55/** Start of memory mapped I/O area for GTA02 */
     56#define GTA02_IOMEM_START  0x48000000
     57/** End of memory mapped I/O area for GTA02 */
     58#define GTA02_IOMEM_END  0x60000000
    5259
    5360/* Page table level 0 entry - "section" format is used
  • mainline/boot/arch/arm32/src/asm.S

    r3.1.12 r1739  
    6060        # before passing control to the copied code.
    6161        #
     62
     63#if defined(MACHINE_gta02)
     64
     65#define CP15_C1_IC              12
     66#define CP15_C1_DC              2
     67#define CP15_C7_SEG_SHIFT       5
     68#define CP15_C7_SEG_SIZE        3
     69#define CP15_C7_IDX_SHIFT       26
     70
     71        # Disable I-cache and D-cache before the kernel is started.
     72        mrc     p15, 0, r4, c1, c0, 0
     73        bic     r4, r4, #(1 << CP15_C1_DC)
     74        bic     r4, r4, #(1 << CP15_C1_IC)
     75        mcr     p15, 0, r4, c1, c0, 0
     76
     77        # Now clean D-cache to guarantee coherency between I-cache and D-cache.
     78
     79        # D-cache clean and invalidate procedure.
     80        # See ARM920T TRM pages 2-17, 4-17.
     81
     82        # Initialize segment
     83        mov     r4, #0
     84        # Initialize index
     851:      mov     r5, #0
     862:      orr     r6, r4, r5
     87        # Clean and invalidate a single line
     88        mcr     p15, 0, r6, c7, c10, 2
     89        # Increment index
     90        add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
     91        cmp     r5, #0
     92        bne     2b
     93        # Increment segment
     94        add     r4, #(1 << CP15_C7_SEG_SHIFT)
     95        tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
     96        beq     1b
     97#endif
     98
    6299        mov pc, r0
  • mainline/boot/arch/arm32/src/mm.c

    r8.1.91 r1739  
    3838#include <arch/mm.h>
    3939
     40/** Check if caching can be enabled for a given memory section.
     41 *
     42 * Memory areas used for I/O are excluded from caching.
     43 * At the moment caching is enabled only on GTA02.
     44 *
     45 * @param section       The section number.
     46 *
     47 * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
     48*/
     49static inline int section_cacheable(pfn_t section)
     50{
     51#ifdef MACHINE_gta02
     52        unsigned long address = section << PTE_SECTION_SHIFT;
     53
     54        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
     55                return 0;
     56        else
     57                return 1;
     58#else
     59        return 0;
     60#endif
     61}
     62
    4063/** Initialize "section" page table entry.
    4164 *
     
    5578        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    5679        pte->bufferable = 1;
    57         pte->cacheable = 0;
     80        pte->cacheable = section_cacheable(frame);
    5881        pte->xn = 0;
    5982        pte->domain = 0;
     
    123146                "ldr r1, =0x00000005\n"
    124147#else
     148#ifdef MACHINE_gta02
     149                /* Mask to enable paging (bit 0),
     150                   D-cache (bit 2), I-cache (bit 12) */
     151                "ldr r1, =0x00001005\n"
     152#else
    125153                /* Mask to enable paging */
    126154                "ldr r1, =0x00000001\n"
     155#endif
    127156#endif
    128157                "orr r0, r0, r1\n"
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