Changeset fb52db8 in mainline


Ignore:
Timestamp:
2010-02-16T16:41:32Z (14 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
dfecf88
Parents:
5ee2384
Message:

make abs32le compile and link
abs32le now "works" (at least compiled with native x86 GCC), but more work on documentation still has to be done

Files:
26 added
13 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/Makefile.inc

    r5ee2384 rfb52db8  
    3030#
    3131
     32BFD = binary
     33
    3234BITS = 32
    3335ENDIANESS = LE
    … …  
    4345        arch/$(KARCH)/src/ddi/ddi.c \
    4446        arch/$(KARCH)/src/smp/smp.c \
     47        arch/$(KARCH)/src/smp/ipi.c \
    4548        arch/$(KARCH)/src/mm/as.c \
    4649        arch/$(KARCH)/src/mm/frame.c \

  • kernel/arch/abs32le/include/asm.h

    r5ee2384 rfb52db8  
    4040#include <config.h>
    4141
    42 extern void interrupt_handlers(void);
    43 
    44 extern void enable_l_apic_in_msr(void);
    45 
    46 
    47 extern void asm_delay_loop(uint32_t);
    48 extern void asm_fake_loop(uint32_t);
    49 
     42static inline void asm_delay_loop(uint32_t usec)
     43{
     44}
    5045
    5146static inline __attribute__((noreturn)) void cpu_halt(void)

  • kernel/arch/abs32le/include/atomic.h

    r5ee2384 rfb52db8  
    8181#define atomic_predec(val)  (atomic_postdec(val) - 1)
    8282
    83 static inline uint32_t test_and_set(atomic_t *val) {
    84         uint32_t v;
    85        
    86         asm volatile (
    87                 "movl $1, %[v]\n"
    88                 "xchgl %[v], %[count]\n"
    89                 : [v] "=r" (v), [count] "+m" (val->count)
    90         );
    91        
    92         return v;
     83static inline uint32_t test_and_set(atomic_t *val)
     84{
     85        uint32_t prev = val->count;
     86        val->count = 1;
     87        return prev;
    9388}
    9489
    95 /** ia32 specific fast spinlock */
    9690static inline void atomic_lock_arch(atomic_t *val)
    9791{
    98         uint32_t tmp;
    99        
    100         preemption_disable();
    101         asm volatile (
    102                 "0:\n"
    103                 "pause\n"        /* Pentium 4's HT love this instruction */
    104                 "mov %[count], %[tmp]\n"
    105                 "testl %[tmp], %[tmp]\n"
    106                 "jnz 0b\n"       /* lightweight looping on locked spinlock */
    107                
    108                 "incl %[tmp]\n"  /* now use the atomic operation */
    109                 "xchgl %[count], %[tmp]\n"
    110                 "testl %[tmp], %[tmp]\n"
    111                 "jnz 0b\n"
    112                 : [count] "+m" (val->count), [tmp] "=&r" (tmp)
    113         );
    114         /*
    115          * Prevent critical section code from bleeding out this way up.
    116          */
    117         CS_ENTER_BARRIER();
     92        do {
     93                while (val->count);
     94        } while (test_and_set(val));
    11895}
    11996

  • kernel/arch/abs32le/include/barrier.h

    r5ee2384 rfb52db8  
    2727 */
    2828
    29 /** @addtogroup ia32
     29/** @addtogroup abs32le
    3030 * @{
    3131 */
    … …  
    3333 */
    3434
    35 #ifndef KERN_ia32_BARRIER_H_
    36 #define KERN_ia32_BARRIER_H_
    37 
    38 /*
    39  * NOTE:
    40  * No barriers for critical section (i.e. spinlock) on IA-32 are needed:
    41  * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
    42  * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
    43  */
     35#ifndef KERN_abs32le_BARRIER_H_
     36#define KERN_abs32le_BARRIER_H_
    4437
    4538/*
    … …  
    4740 */
    4841
    49 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
    50 #define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
     42#define CS_ENTER_BARRIER()
     43#define CS_LEAVE_BARRIER()
    5144
    52 static inline void cpuid_serialization(void)
    53 {
    54         asm volatile (
    55                 "xorl %%eax, %%eax\n"
    56                 "cpuid\n"
    57                 ::: "eax", "ebx", "ecx", "edx", "memory"
    58         );
    59 }
     45#define memory_barrier()
     46#define read_barrier()
     47#define write_barrier()
    6048
    61 #if defined(CONFIG_FENCES_P4)
    62         #define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
    63         #define read_barrier()    asm volatile ("lfence\n" ::: "memory")
    64         #ifdef CONFIG_WEAK_MEMORY
    65                 #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
    66         #else
    67                 #define write_barrier()  asm volatile ("" ::: "memory");
    68         #endif
    69 #elif defined(CONFIG_FENCES_P3)
    70         #define memory_barrier()  cpuid_serialization()
    71         #define read_barrier()    cpuid_serialization()
    72         #ifdef CONFIG_WEAK_MEMORY
    73                 #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
    74         #else
    75                 #define write_barrier()  asm volatile ("" ::: "memory");
    76         #endif
    77 #else
    78         #define memory_barrier()  cpuid_serialization()
    79         #define read_barrier()    cpuid_serialization()
    80         #ifdef CONFIG_WEAK_MEMORY
    81                 #define write_barrier()  cpuid_serialization()
    82         #else
    83                 #define write_barrier()  asm volatile ("" ::: "memory");
    84         #endif
    85 #endif
    86 
    87 /*
    88  * On ia32, the hardware takes care about instruction and data cache coherence,
    89  * even on SMP systems.  We issue a write barrier to be sure that writes
    90  * queueing in the store buffer drain to the memory (even though it would be
    91  * sufficient for them to drain to the D-cache).
    92  */
    93 #define smc_coherence(a)           write_barrier()
    94 #define smc_coherence_block(a, l)  write_barrier()
     49#define smc_coherence(addr)
     50#define smc_coherence_block(addr, size)
    9551
    9652#endif

  • kernel/arch/abs32le/include/context.h

    r5ee2384 rfb52db8  
    4040
    4141#define context_set(ctx, pc, stack, size) \
    42     context_set_generic(ctx, pc, stack, size)
     42        context_set_generic(ctx, pc, stack, size)
    4343
    4444/*

  • kernel/arch/abs32le/include/context_offset.h

    r5ee2384 rfb52db8  
    3737
    3838#define OFFSET_PC  0x00
    39 
    40 #ifdef KERNEL
    41         #define OFFSET_IPL 0x04
    42 #else
    43         #define OFFSET_TLS 0x04
    44 #endif
     39#define OFFSET_IPL 0x04
    4540
    4641#endif

  • kernel/arch/abs32le/include/mm/frame.h

    r5ee2384 rfb52db8  
    4040
    4141#ifdef KERNEL
    42 #ifndef __ASM__
    4342
    4443#include <arch/types.h>
    … …  
    4746extern void physmem_print(void);
    4847
    49 #endif /* __ASM__ */
    5048#endif /* KERNEL */
    5149

  • kernel/arch/abs32le/include/mm/page.h

    r5ee2384 rfb52db8  
    4343#ifdef KERNEL
    4444
    45 #ifndef __ASM__
    46         #define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
    47         #define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
    48 #else
    49         #define KA2PA(x)  ((x) - 0x80000000)
    50         #define PA2KA(x)  ((x) + 0x80000000)
    51 #endif
     45#define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
     46#define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
    5247
    5348/*
    … …  
    122117#define PTE_EXECUTABLE_ARCH(p)  1
    123118
    124 #ifndef __ASM__
    125 
    126119#include <mm/mm.h>
    127120#include <arch/interrupt.h>
    … …  
    129122#include <typedefs.h>
    130123
    131 /* Page fault error codes. */
    132 
    133 /** When bit on this position is 0, the page fault was caused by a not-present
    134  * page.
    135  */
    136 #define PFERR_CODE_P            (1 << 0)
    137 
    138 /** When bit on this position is 1, the page fault was caused by a write. */
    139 #define PFERR_CODE_RW           (1 << 1)
    140 
    141 /** When bit on this position is 1, the page fault was caused in user mode. */
    142 #define PFERR_CODE_US           (1 << 2)
    143 
    144 /** When bit on this position is 1, a reserved bit was set in page directory. */
    145 #define PFERR_CODE_RSVD         (1 << 3)       
    146 
    147124/** Page Table Entry. */
    148125typedef struct {
    149         unsigned present : 1;
    150         unsigned writeable : 1;
    151         unsigned uaccessible : 1;
    152         unsigned page_write_through : 1;
    153         unsigned page_cache_disable : 1;
    154         unsigned accessed : 1;
    155         unsigned dirty : 1;
    156         unsigned pat : 1;
    157         unsigned global : 1;
    158         unsigned soft_valid : 1;        /**< Valid content even if the present bit is not set. */
    159         unsigned avl : 2;
    160         unsigned frame_address : 20;
    161 } __attribute__ ((packed)) pte_t;
     126        unsigned int present : 1;
     127        unsigned int writeable : 1;
     128        unsigned int uaccessible : 1;
     129        unsigned int page_write_through : 1;
     130        unsigned int page_cache_disable : 1;
     131        unsigned int accessed : 1;
     132        unsigned int dirty : 1;
     133        unsigned int pat : 1;
     134        unsigned int global : 1;
     135       
     136        /** Valid content even if the present bit is not set. */
     137        unsigned int soft_valid : 1;
     138        unsigned int avl : 2;
     139        unsigned int frame_address : 20;
     140} __attribute__((packed)) pte_t;
    162141
    163142static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    … …  
    192171
    193172extern void page_arch_init(void);
    194 extern void page_fault(int n, istate_t *istate);
    195 
    196 #endif /* __ASM__ */
     173extern void page_fault(int, istate_t *);
    197174
    198175#endif /* KERNEL */

  • kernel/arch/abs32le/src/abs32le.c

    r5ee2384 rfb52db8  
    3535#include <arch.h>
    3636#include <arch/types.h>
    37 #include <arch/context.h>
    3837#include <arch/interrupt.h>
    3938#include <arch/asm.h>
    … …  
    4140#include <func.h>
    4241#include <config.h>
     42#include <errno.h>
    4343#include <context.h>
     44#include <fpu_context.h>
    4445#include <interrupt.h>
     46#include <syscall/copy.h>
    4547#include <ddi/irq.h>
    4648#include <proc/thread.h>
    … …  
    4951#include <sysinfo/sysinfo.h>
    5052#include <memstr.h>
     53
     54char memcpy_from_uspace_failover_address;
     55char memcpy_to_uspace_failover_address;
    5156
    5257void arch_pre_mm_init(void)
    … …  
    8388unative_t sys_tls_set(unative_t addr)
    8489{
    85         return 0;
     90        return EOK;
    8691}
    8792
    … …  
    109114}
    110115
    111 void memsetb(void *dst, size_t cnt, uint8_t val)
    112 {
    113         _memsetb(dst, cnt, val);
    114 }
    115 
    116 void memsetw(void *dst, size_t cnt, uint16_t val)
    117 {
    118         _memsetw(dst, cnt, val);
    119 }
    120 
    121116void panic_printf(char *fmt, ...)
    122117{
    … …  
    140135}
    141136
     137void fpu_init(void)
     138{
     139}
     140
     141void fpu_context_save(fpu_context_t *ctx)
     142{
     143}
     144
     145void fpu_context_restore(fpu_context_t *ctx)
     146{
     147}
     148
     149int memcpy_from_uspace(void *dst, const void *uspace_src, size_t size)
     150{
     151        return EOK;
     152}
     153
     154int memcpy_to_uspace(void *uspace_dst, const void *src, size_t size)
     155{
     156        return EOK;
     157}
     158
    142159/** @}
    143160 */

  • kernel/arch/abs32le/src/debug/stacktrace.c

    r5ee2384 rfb52db8  
    4040bool kernel_frame_pointer_validate(uintptr_t fp)
    4141{
    42         return true;;
     42        return true;
    4343}
    4444

  • uspace/lib/libc/include/stacktrace.h

    r5ee2384 rfb52db8  
    5757extern void stacktrace_prepare(void);
    5858extern uintptr_t stacktrace_fp_get(void);
    59 extern uintptr_t stacktrace_pc_get();
     59extern uintptr_t stacktrace_pc_get(void);
    6060
    6161#endif

  • uspace/srv/hid/kbd/Makefile.build

    r5ee2384 rfb52db8  
    150150endif
    151151
     152ifeq ($(UARCH),abs32le)
     153        SOURCES += \
     154                port/dummy.c \
     155                ctl/pc.c
     156endif
     157
    152158OBJECTS := $(addsuffix .o,$(basename $(SOURCES)))
    153159

  • uspace/srv/loader/include/arch.h

    r5ee2384 rfb52db8  
    3737#define LOADER_ARCH_H_
    3838
    39 void program_run(void *entry_point, void *pcb);
     39extern void program_run(void *entry_point, void *pcb);
    4040
    4141#endif
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