Changeset f6062f15 in mainline


Ignore:
Timestamp:
2011-11-11T17:45:07Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update
Children:
751d17a2
Parents:
4440581
Message:

sb16: DMAC fix register addresses. Reset DMAC on init.

Improve debug messages.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/audio/sb16/dma_controller.c

    r4440581 rf6062f15  
    8585
    8686        uint8_t flip_flop;
     87        /* Master reset sets Flip-Flop low, clears status,
     88         * sets all mask bits on */
    8789        uint8_t master_reset; /* Intermediate is not implemented on PCs */
    8890        uint8_t mask_reset;
    89 /* Master reset sets Flip-Flop low, clears status,sets all mask bits on */
    9091
    9192        uint8_t multi_mask;
     
    123124        uint8_t flip_flop;
    124125        uint8_t reservedc;
    125         uint8_t master_reset_intermediate;
     126        uint8_t master_reset;
    126127        uint8_t reservedd;
    127128        uint8_t multi_mask;
     
    214215                return EIO;
    215216        controller->initialized = true;
     217
     218        pio_write_8(&controller->second->master_reset, 0xff);
     219        pio_write_8(&controller->first->master_reset, 0xff);
     220
     221
    216222        return EOK;
    217223}
     
    232238
    233239        /* 16 bit transfers are a bit special */
    234         ddf_log_debug("Unspoiled address and size: %p(%zu).\n", pa, size);
     240        ddf_log_debug("Unspoiled address: %p and size: %zu.\n", pa, size);
    235241        if (channel > 4) {
    236242                /* Size is the count of 16bit words */
     
    253259        /* Set mode */
    254260        value = DMA_MODE_CHAN_TO_REG(channel) | mode;
     261        ddf_log_verbose("Writing mode byte: %p:%hhx.\n",
     262            dma_channel.mode_address, value);
    255263        pio_write_8(dma_channel.mode_address, value);
    256264
     
    260268        /* Low byte */
    261269        value = pa & 0xff;
    262         ddf_log_verbose("Writing address low byte: %hhx.\n", value);
     270        ddf_log_verbose("Writing address low byte: %p:%hhx.\n",
     271            dma_channel.offset_reg_address, value);
    263272        pio_write_8(dma_channel.offset_reg_address, value);
    264273
    265274        /* High byte */
    266275        value = (pa >> 8) & 0xff;
    267         ddf_log_verbose("Writing address high byte: %hhx.\n", value);
     276        ddf_log_verbose("Writing address high byte: %p:%hhx.\n",
     277            dma_channel.offset_reg_address, value);
    268278        pio_write_8(dma_channel.offset_reg_address, value);
    269279
    270280        /* Page address - third byte */
    271281        value = (pa >> 16) & 0xff;
    272         ddf_log_verbose("Writing address page byte: %hhx.\n", value);
    273         pio_write_8(dma_channel.offset_reg_address, value);
     282        ddf_log_verbose("Writing address page byte: %p:%hhx.\n",
     283            dma_channel.page_reg_address, value);
     284        pio_write_8(dma_channel.page_reg_address, value);
    274285
    275286        /* Set size -- reset flip-flop */
     
    278289        /* Low byte */
    279290        value = (size - 1) & 0xff;
    280         ddf_log_verbose("Writing size low byte: %hhx.\n", value);
    281         pio_write_8(dma_channel.offset_reg_address, value);
     291        ddf_log_verbose("Writing size low byte: %p:%hhx.\n",
     292            dma_channel.size_reg_address, value);
     293        pio_write_8(dma_channel.size_reg_address, value);
    282294
    283295        /* High byte */
    284296        value = ((size - 1) >> 8) & 0xff;
    285         ddf_log_verbose("Writing size high byte: %hhx.\n", value);
    286         pio_write_8(dma_channel.offset_reg_address, value);
     297        ddf_log_verbose("Writing size high byte: %p:%hhx.\n",
     298            dma_channel.size_reg_address, value);
     299        pio_write_8(dma_channel.size_reg_address, value);
    287300
    288301        /* Unmask DMA request */
Note: See TracChangeset for help on using the changeset viewer.