Changeset f58154c5 in mainline for uspace/drv/ohci/hc.c

Timestamp:

2011-05-18T10:59:50Z (13 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

17fc40c

Parents:

b2995c3 (diff), aeca5a3 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Minor fixes and comments

UHCI: use provided barrier defines (buffer allocator should be able to use cacheable memory)
libusb: make usb enumeration routine follow USB spec more closely (wait periods)
OHCI: handle hw errors
OHCI: use provided barrier defines (buffer allocator should be able to use cacheable memory)
OHCI: reduce maximum buffer size for one transaction, this relaxes requirements on allocator providing hw accessible buffers.(memory does not have to be continuous) The only requirement that stays is the 32bit pointers limit.

File:

• uspace/drv/ohci/hc.c (modified) (4 diffs)

uspace/drv/ohci/hc.c

@@ -293 +293 @@
                 rh_interrupt(&instance->rh);
 
-
         if (status & I_WDH) {
                 fibril_mutex_lock(&instance->guard);
@@ -316 +315 @@
                 fibril_mutex_unlock(&instance->guard);
         }
+
+        if (status & I_UE) {
+                hc_start_hw(instance);
+        }
+
 }
 /*----------------------------------------------------------------------------*/
@@ -450 +454 @@
 {
         assert(instance);
-
 #define SETUP_ENDPOINT_LIST(type) \
 do { \
@@ -458 +461 @@
                 usb_log_error("Failed(%d) to setup %s endpoint list.\n", \
                     ret, name); \
-                endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]); \
+                endpoint_list_fini(&instance->lists[USB_TRANSFER_ISOCHRONOUS]);\
                 endpoint_list_fini(&instance->lists[USB_TRANSFER_INTERRUPT]); \
                 endpoint_list_fini(&instance->lists[USB_TRANSFER_CONTROL]); \