Changeset f4c87aa9 in mainline


Ignore:
Timestamp:
2011-02-16T18:45:36Z (13 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9013ad3
Parents:
2e85b3c
Message:

Few fixes and cleanup

Location:
uspace/drv/uhci-hcd
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/uhci-hcd/uhci.c

    r2e85b3c rf4c87aa9  
    4141
    4242static int uhci_init_transfer_lists(uhci_t *instance);
     43static int uhci_init_mem_structures(uhci_t *instance);
     44static void uhci_init_hw(uhci_t *instance);
     45
    4346static int uhci_clean_finished(void *arg);
    4447static int uhci_debug_checker(void *arg);
     48
    4549static bool allowed_usb_packet(
    4650        bool low_speed, usb_transfer_type_t, size_t size);
    4751
    48 int uhci_init(uhci_t *instance, void *regs, size_t reg_size)
    49 {
    50 #define CHECK_RET_RETURN(message...) \
     52#define CHECK_RET_RETURN(ret, message...) \
    5153        if (ret != EOK) { \
    5254                usb_log_error(message); \
    … …  
    5456        } else (void) 0
    5557
    56         /* init address keeper(libusb) */
    57         usb_address_keeping_init(&instance->address_manager, USB11_ADDRESS_MAX);
    58         usb_log_debug("Initialized address manager.\n");
     58int uhci_init(uhci_t *instance, void *regs, size_t reg_size)
     59{
     60        int ret = uhci_init_mem_structures(instance);
     61        CHECK_RET_RETURN(ret, "Failed to initialize memory structures.\n");
    5962
    6063        /* allow access to hc control registers */
    6164        regs_t *io;
    6265        assert(reg_size >= sizeof(regs_t));
    63         int ret = pio_enable(regs, reg_size, (void**)&io);
    64         CHECK_RET_RETURN("Failed to gain access to registers at %p.\n", io);
     66        ret = pio_enable(regs, reg_size, (void**)&io);
     67        CHECK_RET_RETURN(ret, "Failed to gain access to registers at %p.\n", io);
    6568        instance->registers = io;
    6669        usb_log_debug("Device registers accessible.\n");
    6770
     71        instance->cleaner = fibril_create(uhci_clean_finished, instance);
     72        fibril_add_ready(instance->cleaner);
     73
     74        instance->debug_checker = fibril_create(uhci_debug_checker, instance);
     75        fibril_add_ready(instance->debug_checker);
     76
     77        uhci_init_hw(instance);
     78
     79        return EOK;
     80}
     81/*----------------------------------------------------------------------------*/
     82void uhci_init_hw(uhci_t *instance)
     83{
     84        const uintptr_t pa = (uintptr_t)addr_to_phys(instance->frame_list);
     85        pio_write_32(&instance->registers->flbaseadd, (uint32_t)pa);
     86
     87        /* Start the hc with large(64B) packet FSBR */
     88        pio_write_16(&instance->registers->usbcmd,
     89            UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET);
     90        usb_log_debug("Started UHCI HC.\n");
     91}
     92/*----------------------------------------------------------------------------*/
     93int uhci_init_mem_structures(uhci_t *instance)
     94{
     95        assert(instance);
    6896        /* init transfer lists */
    69         ret = uhci_init_transfer_lists(instance);
    70         CHECK_RET_RETURN("Failed to initialize transfer lists.\n");
     97        int ret = uhci_init_transfer_lists(instance);
     98        CHECK_RET_RETURN(ret, "Failed to initialize transfer lists.\n");
    7199        usb_log_debug("Transfer lists initialized.\n");
    72100
    73 
     101        /* frame list initialization */
    74102        usb_log_debug("Initializing frame list.\n");
    75103        instance->frame_list = get_page();
    76104        ret = instance ? EOK : ENOMEM;
    77         CHECK_RET_RETURN("Failed to get frame list page.\n");
     105        CHECK_RET_RETURN(ret, "Failed to get frame list page.\n");
    78106
    79107        /* initialize all frames to point to the first queue head */
    … …  
    86114        }
    87115
    88         const uintptr_t pa = (uintptr_t)addr_to_phys(instance->frame_list);
    89         pio_write_32(&instance->registers->flbaseadd, (uint32_t)pa);
    90 
    91         list_initialize(&instance->batch_list);
    92         fibril_mutex_initialize(&instance->batch_list_mutex);
    93 
    94         instance->cleaner = fibril_create(uhci_clean_finished, instance);
    95         fibril_add_ready(instance->cleaner);
    96 
    97         instance->debug_checker = fibril_create(uhci_debug_checker, instance);
    98         fibril_add_ready(instance->debug_checker);
    99 
    100         /* Start the hc with large(64B) packet FSBR */
    101         pio_write_16(&instance->registers->usbcmd,
    102             UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET);
    103         usb_log_debug("Started UHCI HC.\n");
    104 
    105         uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
    106         cmd |= UHCI_CMD_DEBUG;
    107         pio_write_16(&instance->registers->usbcmd, cmd);
     116        /* init address keeper(libusb) */
     117        usb_address_keeping_init(&instance->address_manager, USB11_ADDRESS_MAX);
     118        usb_log_debug("Initialized address manager.\n");
    108119
    109120        return EOK;
    … …  
    114125        assert(instance);
    115126
    116         /* initialize */
     127        /* initialize TODO: check errors */
    117128        int ret;
    118129        ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
    … …  
    146157        instance->transfers[1][USB_TRANSFER_CONTROL] =
    147158          &instance->transfers_control_slow;
    148         instance->transfers[0][USB_TRANSFER_CONTROL] =
    149           &instance->transfers_control_full;
     159        instance->transfers[0][USB_TRANSFER_BULK] =
     160          &instance->transfers_bulk_full;
    150161
    151162        return EOK;

  • uspace/drv/uhci-hcd/uhci.h

    r2e85b3c rf4c87aa9  
    8181        link_pointer_t *frame_list;
    8282
    83         link_t batch_list;
    84         fibril_mutex_t batch_list_mutex;
    85 
    8683        transfer_list_t transfers_bulk_full;
    8784        transfer_list_t transfers_control_full;
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