Index: uspace/srv/hw/netif/dp8390/dp8390.h
===================================================================
--- uspace/srv/hw/netif/dp8390/dp8390.h	(revision b404a98258ad59f7e2c9104938c667be48547dca)
+++ uspace/srv/hw/netif/dp8390/dp8390.h	(revision f40a1e24252e9904e01ba889c8b1edbbe5cc9d63)
@@ -38,5 +38,5 @@
  */
 
-/** @addtogroup dp8390
+/** @addtogroup ne2000
  *  @{
  */
@@ -49,9 +49,15 @@
 #define __NET_NETIF_DP8390_H__
 
+#include <fibril_synch.h>
 #include <net/packet.h>
-#include "dp8390_port.h"
+
+/** Module name */
+#define NAME  "ne2000"
 
 /** Input/output size */
-#define DP8390_IO_SIZE  0x0020
+#define NE2K_IO_SIZE  0x0020
+
+/** Ethernet address length */
+#define ETH_ADDR  6
 
 /* National Semiconductor DP8390 Network Interface Controller. */
@@ -105,187 +111,128 @@
 #define DP_MAR7  0x0f  /**< Multicast Address Register 7 */
 
-/* Bits in dp_cr */
-#define CR_STP		0x01	/* Stop: software reset              */
-#define CR_STA		0x02	/* Start: activate NIC               */
-#define CR_TXP		0x04	/* Transmit Packet                   */
-#define CR_DMA		0x38	/* Mask for DMA control              */
-#define CR_DM_NOP	0x00	/* DMA: No Operation                 */
-#define CR_DM_RR	0x08	/* DMA: Remote Read                  */
-#define CR_DM_RW	0x10	/* DMA: Remote Write                 */
-#define CR_DM_SP	0x18	/* DMA: Send Packet                  */
-#define CR_DM_ABORT	0x20	/* DMA: Abort Remote DMA Operation   */
-#define CR_PS		0xC0	/* Mask for Page Select              */
-#define CR_PS_P0	0x00	/* Register Page 0                   */
-#define CR_PS_P1	0x40	/* Register Page 1                   */
-#define CR_PS_P2	0x80	/* Register Page 2                   */
-#define CR_PS_T1	0xC0	/* Test Mode Register Map            */
-
-/* Bits in dp_isr */
-#define ISR_PRX		0x01	/* Packet Received with no errors    */
-#define ISR_PTX		0x02	/* Packet Transmitted with no errors */
-#define ISR_RXE		0x04	/* Receive Error                     */
-#define ISR_TXE		0x08	/* Transmit Error                    */
-#define ISR_OVW		0x10	/* Overwrite Warning                 */
-#define ISR_CNT		0x20	/* Counter Overflow                  */
-#define ISR_RDC		0x40	/* Remote DMA Complete               */
-#define ISR_RST		0x80	/* Reset Status                      */
-
-/* Bits in dp_imr */
-#define IMR_PRXE	0x01	/* Packet Received iEnable           */
-#define IMR_PTXE	0x02	/* Packet Transmitted iEnable        */
-#define IMR_RXEE	0x04	/* Receive Error iEnable             */
-#define IMR_TXEE	0x08	/* Transmit Error iEnable            */
-#define IMR_OVWE	0x10	/* Overwrite Warning iEnable         */
-#define IMR_CNTE	0x20	/* Counter Overflow iEnable          */
-#define IMR_RDCE	0x40	/* DMA Complete iEnable              */
-
-/* Bits in dp_dcr */
-#define DCR_WTS		0x01	/* Word Transfer Select              */
-#define DCR_BYTEWIDE	0x00	/* WTS: byte wide transfers          */
-#define DCR_WORDWIDE	0x01	/* WTS: word wide transfers          */
-#define DCR_BOS		0x02	/* Byte Order Select                 */
-#define DCR_LTLENDIAN	0x00	/* BOS: Little Endian                */
-#define DCR_BIGENDIAN	0x02	/* BOS: Big Endian                   */
-#define DCR_LAS		0x04	/* Long Address Select               */
-#define DCR_BMS		0x08	/* Burst Mode Select
-				 * Called Loopback Select (LS) in 
-				 * later manuals. Should be set.     */
-#define DCR_AR		0x10	/* Autoinitialize Remote             */
-#define DCR_FTS		0x60	/* Fifo Threshold Select             */
-#define DCR_2BYTES	0x00	/* 2 bytes                           */
-#define DCR_4BYTES	0x40	/* 4 bytes                           */
-#define DCR_8BYTES	0x20	/* 8 bytes                           */
-#define DCR_12BYTES	0x60	/* 12 bytes                          */
-
-/* Bits in dp_tcr */
-#define TCR_CRC		0x01	/* Inhibit CRC                       */
-#define TCR_ELC		0x06	/* Encoded Loopback Control          */
-#define TCR_NORMAL	0x00	/* ELC: Normal Operation             */
-#define TCR_INTERNAL	0x02	/* ELC: Internal Loopback            */
-#define TCR_0EXTERNAL	0x04	/* ELC: External Loopback LPBK=0     */
-#define TCR_1EXTERNAL	0x06	/* ELC: External Loopback LPBK=1     */
-#define TCR_ATD		0x08	/* Auto Transmit Disable             */
-#define TCR_OFST	0x10	/* Collision Offset Enable (be nice) */
-
-/* Bits in dp_tsr */
-#define TSR_PTX		0x01	/* Packet Transmitted (without error)*/
-#define TSR_DFR		0x02	/* Transmit Deferred, reserved in
-				 * later manuals.		     */
-#define TSR_COL		0x04	/* Transmit Collided                 */
-#define TSR_ABT		0x08	/* Transmit Aborted                  */
-#define TSR_CRS		0x10	/* Carrier Sense Lost                */
-#define TSR_FU		0x20	/* FIFO Underrun                     */
-#define TSR_CDH		0x40	/* CD Heartbeat                      */
-#define TSR_OWC		0x80	/* Out of Window Collision           */
-
-/* Bits in tp_rcr */
-#define RCR_SEP		0x01	/* Save Errored Packets              */
-#define RCR_AR		0x02	/* Accept Runt Packets               */
-#define RCR_AB		0x04	/* Accept Broadcast                  */
-#define RCR_AM		0x08	/* Accept Multicast                  */
-#define RCR_PRO		0x10	/* Physical Promiscuous              */
-#define RCR_MON		0x20	/* Monitor Mode                      */
-
-/* Bits in dp_rsr */
-#define RSR_PRX		0x01	/* Packet Received Intact            */
-#define RSR_CRC		0x02	/* CRC Error                         */
-#define RSR_FAE		0x04	/* Frame Alignment Error             */
-#define RSR_FO		0x08	/* FIFO Overrun                      */
-#define RSR_MPA		0x10	/* Missed Packet                     */
-#define RSR_PHY		0x20	/* Multicast Address Match           */
-#define RSR_DIS		0x40	/* Receiver Disabled                 */
-#define RSR_DFR		0x80	/* In later manuals: Deferring       */
-
-/** Type definition of the receive header
- *
- */
-typedef struct dp_rcvhdr {
-	/** Copy of rsr */
-	uint8_t dr_status;
-	
-	/** Pointer to next packet */
-	uint8_t dr_next;
-	
-	/** Receive Byte Count Low */
-	uint8_t dr_rbcl;
-	
-	/** Receive Byte Count High */
-	uint8_t dr_rbch;
-} dp_rcvhdr_t;
-
-/** Page size */
-#define DP_PAGESIZE  256
-
-/** Read 1 byte from the zero page register.
- *  @param[in] dep The network interface structure.
- *  @param[in] reg The register offset.
- *  @returns The read value.
- */
-#define inb_reg0(dep, reg)  (inb(dep->de_dp8390_port + reg))
-
-/** Write 1 byte zero page register.
- *  @param[in] dep The network interface structure.
- *  @param[in] reg The register offset.
- *  @param[in] data The value to be written.
- */
-#define outb_reg0(dep, reg, data)  (outb(dep->de_dp8390_port + reg, data))
-
-/** Read 1 byte from the first page register.
- *  @param[in] dep The network interface structure.
- *  @param[in] reg The register offset.
- *  @returns The read value.
- */
-#define inb_reg1(dep, reg)  (inb(dep->de_dp8390_port + reg))
-
-/** Write 1 byte first page register.
- *  @param[in] dep The network interface structure.
- *  @param[in] reg The register offset.
- *  @param[in] data The value to be written.
- */
-#define outb_reg1(dep, reg, data)  (outb(dep->de_dp8390_port + reg, data))
-
-#define SENDQ_NR     1  /* Maximum size of the send queue */
-#define SENDQ_PAGES  6  /* 6 * DP_PAGESIZE >= 1514 bytes */
-
-typedef struct dpeth {
-	/*
-	 * The de_base_port field is the starting point of the probe.
-	 * The conf routine also fills de_irq. If the probe
-	 * routine knows the irq and/or memory address because they are
-	 * hardwired in the board, the probe should modify these fields.
-	 */
-	port_t de_base_port;
-	int de_irq;
-	
-	ether_addr_t de_address;
-	port_t de_dp8390_port;
-	port_t de_data_port;
-	int de_16bit;
-	long de_ramsize;
-	int de_offset_page;
-	int de_startpage;
-	int de_stoppage;
-	
-	/* Do it yourself send queue */
-	struct sendq {
-		int sq_filled;    /* this buffer contains a packet */
-		int sq_size;      /* with this size */
-		int sq_sendpage;  /* starting page of the buffer */
-	} de_sendq[SENDQ_NR];
-	
-	int de_sendq_nr;
-	int de_sendq_head;  /* Enqueue at the head */
-	int de_sendq_tail;  /* Dequeue at the tail */
-	
-	/* Fields for internal use by the dp8390 driver. */
-	eth_stat_t de_stat;
-	
-	/* Driver flags */
+/* Bits in Command Register */
+#define CR_STP       0x01  /**< Stop (software reset) */
+#define CR_STA       0x02  /**< Start (activate NIC) */
+#define CR_TXP       0x04  /**< Transmit Packet */
+#define CR_DMA       0x38  /**< Mask for DMA control */
+#define CR_DM_NOP    0x00  /**< DMA: No Operation */
+#define CR_DM_RR     0x08  /**< DMA: Remote Read */
+#define CR_DM_RW     0x10  /**< DMA: Remote Write */
+#define CR_DM_SP     0x18  /**< DMA: Send Packet */
+#define CR_DM_ABORT  0x20  /**< DMA: Abort Remote DMA Operation */
+#define CR_PS        0xc0  /**< Mask for Page Select */
+#define CR_PS_P0     0x00  /**< Register Page 0 */
+#define CR_PS_P1     0x40  /**< Register Page 1 */
+#define CR_PS_P2     0x80  /**< Register Page 2 */
+#define CR_PS_T1     0xc0  /**< Test Mode Register Map */
+
+/* Bits in Interrupt State Register */
+#define ISR_PRX  0x01  /**< Packet Received with no errors */
+#define ISR_PTX  0x02  /**< Packet Transmitted with no errors */
+#define ISR_RXE  0x04  /**< Receive Error */
+#define ISR_TXE  0x08  /**< Transmit Error */
+#define ISR_OVW  0x10  /**< Overwrite Warning */
+#define ISR_CNT  0x20  /**< Counter Overflow */
+#define ISR_RDC  0x40  /**< Remote DMA Complete */
+#define ISR_RST  0x80  /**< Reset Status */
+
+/* Bits in Interrupt Mask Register */
+#define IMR_PRXE  0x01  /**< Packet Received Interrupt Enable */
+#define IMR_PTXE  0x02  /**< Packet Transmitted Interrupt Enable */
+#define IMR_RXEE  0x04  /**< Receive Error Interrupt Enable */
+#define IMR_TXEE  0x08  /**< Transmit Error Interrupt Enable */
+#define IMR_OVWE  0x10  /**< Overwrite Warning Interrupt Enable */
+#define IMR_CNTE  0x20  /**< Counter Overflow Interrupt Enable */
+#define IMR_RDCE  0x40  /**< DMA Complete Interrupt Enable */
+
+/* Bits in Data Configuration Register */
+#define DCR_WTS        0x01  /**< Word Transfer Select */
+#define DCR_BYTEWIDE   0x00  /**< WTS: byte wide transfers */
+#define DCR_WORDWIDE   0x01  /**< WTS: word wide transfers */
+#define DCR_BOS        0x02  /**< Byte Order Select */
+#define DCR_LTLENDIAN  0x00  /**< BOS: Little Endian */
+#define DCR_BIGENDIAN  0x02  /**< BOS: Big Endian */
+#define DCR_LAS        0x04  /**< Long Address Select */
+#define DCR_BMS        0x08  /**< Burst Mode Select */
+#define DCR_AR         0x10  /**< Autoinitialize Remote */
+#define DCR_FTS        0x60  /**< Fifo Threshold Select */
+#define DCR_2BYTES     0x00  /**< 2 bytes */
+#define DCR_4BYTES     0x40  /**< 4 bytes */
+#define DCR_8BYTES     0x20  /**< 8 bytes */
+#define DCR_12BYTES    0x60  /**< 12 bytes */
+
+/* Bits in Transmit Configuration Register */
+#define TCR_CRC        0x01  /**< Inhibit CRC */
+#define TCR_ELC        0x06  /**< Encoded Loopback Control */
+#define TCR_NORMAL     0x00  /**< ELC: Normal Operation */
+#define TCR_INTERNAL   0x02  /**< ELC: Internal Loopback */
+#define TCR_0EXTERNAL  0x04  /**< ELC: External Loopback LPBK=0 */
+#define TCR_1EXTERNAL  0x06  /**< ELC: External Loopback LPBK=1 */
+#define TCR_ATD        0x08  /**< Auto Transmit Disable */
+#define TCR_OFST       0x10  /**< Collision Offset Enable (be nice) */
+
+/* Bits in Interrupt Status Register */
+#define TSR_PTX  0x01  /**< Packet Transmitted (without error) */
+#define TSR_DFR  0x02  /**< Transmit Deferred (reserved) */
+#define TSR_COL  0x04  /**< Transmit Collided */
+#define TSR_ABT  0x08  /**< Transmit Aborted */
+#define TSR_CRS  0x10  /**< Carrier Sense Lost */
+#define TSR_FU   0x20  /**< FIFO Underrun */
+#define TSR_CDH  0x40  /**< CD Heartbeat */
+#define TSR_OWC  0x80  /**< Out of Window Collision */
+
+/* Bits in Receive Configuration Register */
+#define RCR_SEP  0x01  /**< Save Errored Packets */
+#define RCR_AR   0x02  /**< Accept Runt Packets */
+#define RCR_AB   0x04  /**< Accept Broadcast */
+#define RCR_AM   0x08  /**< Accept Multicast */
+#define RCR_PRO  0x10  /**< Physical Promiscuous */
+#define RCR_MON  0x20  /**< Monitor Mode */
+
+/* Bits in Receive Status Register */
+#define RSR_PRX  0x01  /**< Packet Received Intact */
+#define RSR_CRC  0x02  /**< CRC Error */
+#define RSR_FAE  0x04  /**< Frame Alignment Error */
+#define RSR_FO   0x08  /**< FIFO Overrun */
+#define RSR_MPA  0x10  /**< Missed Packet */
+#define RSR_PHY  0x20  /**< Multicast Address Match */
+#define RSR_DIS  0x40  /**< Receiver Disabled */
+#define RSR_DFR  0x80  /**< In later manuals: Deferring */
+
+typedef struct {
+	/* Device configuration */
+	void *port;
+	void *data_port;
+	int irq;
+	uint8_t mac[ETH_ADDR];
+	
+	uint8_t start_page;  /**< Ring buffer start page */
+	uint8_t stop_page;   /**< Ring buffer stop page */
+	
+	/* Send queue */
+	struct {
+		bool dirty;    /**< Buffer contains a packet */
+		size_t size;   /**< Packet size */
+		uint8_t page;  /**< Starting page of the buffer */
+	} sq;
+	fibril_mutex_t sq_mutex;
+	fibril_condvar_t sq_cv;
+	
+	/* Driver run-time variables */
+	bool probed;
 	bool up;
-	bool enabled;
-	bool stopped;
-	bool sending;
-	bool send_avail;
-} dpeth_t;
+	
+	/* Device statistics */
+	device_stats_t stats;
+	uint64_t misses;     /**< Receive frame misses */
+	uint64_t underruns;  /**< FIFO underruns */
+	uint64_t overruns;   /**< FIFO overruns */
+} ne2k_t;
+
+extern int ne2k_probe(ne2k_t *, void *, int);
+extern int ne2k_up(ne2k_t *);
+extern void ne2k_down(ne2k_t *);
+extern void ne2k_send(ne2k_t *, packet_t *);
+extern void ne2k_interrupt(ne2k_t *, uint8_t isr, int, device_id_t);
 
 #endif
