Ignore:
Timestamp:
2010-10-19T20:55:53Z (14 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a93d79a
Parents:
1882525 (diff), a7a85d16 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

    r1882525 rf14291b  
    4040#include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
    4141#include <console/chardev.h>
     42#include <console/console.h>
     43#include <ddi/device.h>
    4244#include <arch/asm.h>
    4345#include <mm/slab.h>
    44 #include <console/console.h>
    4546#include <sysinfo/sysinfo.h>
    4647#include <str.h>
    4748
    48 /** S3C24xx UART register offsets */
    49 #define S3C24XX_UTRSTAT         0x10
    50 #define S3C24XX_UTXH            0x20
    51 
    52 /* Bits in UTXH register */
    53 #define S3C24XX_UTXH_TX_EMPTY   0x4
    54 
    55 typedef struct {
    56         ioport8_t *base;
    57 } s3c24xx_uart_instance_t;
    58 
    5949static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
    6050{
    61         s3c24xx_uart_instance_t *instance =
    62             (s3c24xx_uart_instance_t *) dev->data;
    63         ioport32_t *utrstat, *utxh;
     51        s3c24xx_uart_t *uart =
     52            (s3c24xx_uart_t *) dev->data;
    6453
    65         utrstat = (ioport32_t *) (instance->base + S3C24XX_UTRSTAT);
    66         utxh = (ioport32_t *) (instance->base + S3C24XX_UTXH);
    67 
    68         /* Wait for transmitter to be empty. */
    69         while ((pio_read_32(utrstat) & S3C24XX_UTXH_TX_EMPTY) == 0)
     54        /* Wait for space becoming available in Tx FIFO. */
     55        while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
    7056                ;
    7157
    72         pio_write_32(utxh, byte);
     58        pio_write_32(&uart->io->utxh, byte);
    7359}
    7460
     
    8672}
    8773
     74static irq_ownership_t s3c24xx_uart_claim(irq_t *irq)
     75{
     76        return IRQ_ACCEPT;
     77}
     78
     79static void s3c24xx_uart_irq_handler(irq_t *irq)
     80{
     81        s3c24xx_uart_t *uart = irq->instance;
     82
     83        while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
     84                uint32_t data = pio_read_32(&uart->io->urxh);
     85                pio_read_32(&uart->io->uerstat);
     86                indev_push_character(uart->indev, data & 0xff);
     87        }
     88}
     89
    8890static outdev_operations_t s3c24xx_uart_ops = {
    8991        .write = s3c24xx_uart_putchar,
     
    9193};
    9294
    93 outdev_t *s3c24xx_uart_init(ioport8_t *base)
     95outdev_t *s3c24xx_uart_init(s3c24xx_uart_io_t *io, inr_t inr)
    9496{
    9597        outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
     
    9799                return NULL;
    98100
    99         s3c24xx_uart_instance_t *instance =
    100             malloc(sizeof(s3c24xx_uart_instance_t), FRAME_ATOMIC);
    101         if (!instance) {
     101        s3c24xx_uart_t *uart =
     102            malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC);
     103        if (!uart) {
    102104                free(uart_dev);
    103105                return NULL;
     
    105107
    106108        outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops);
    107         uart_dev->data = instance;
     109        uart_dev->data = uart;
    108110
    109         instance->base = base;
     111        uart->io = io;
     112        uart->indev = NULL;
     113
     114        /* Initialize IRQ structure. */
     115        irq_initialize(&uart->irq);
     116        uart->irq.devno = device_assign_devno();
     117        uart->irq.inr = inr;
     118        uart->irq.claim = s3c24xx_uart_claim;
     119        uart->irq.handler = s3c24xx_uart_irq_handler;
     120        uart->irq.instance = uart;
     121
     122        /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
     123        pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
     124            UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
     125
     126        /* Set RX interrupt to pulse mode */
     127        pio_write_32(&uart->io->ucon,
     128            pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
    110129
    111130        if (!fb_exported) {
     
    116135                sysinfo_set_item_val("fb", NULL, true);
    117136                sysinfo_set_item_val("fb.kind", NULL, 3);
    118                 sysinfo_set_item_val("fb.address.physical", NULL, KA2PA(base));
     137                sysinfo_set_item_val("fb.address.physical", NULL, KA2PA(io));
    119138
    120139                fb_exported = true;
     
    124143}
    125144
     145void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev)
     146{
     147        ASSERT(uart);
     148        ASSERT(indev);
     149
     150        uart->indev = indev;
     151        irq_register(&uart->irq);
     152}
     153
    126154/** @}
    127155 */
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