Changeset ef1a3a8 in mainline for uspace/drv/bus/usb/xhci/hw_struct/context.h

Timestamp:

2017-10-29T11:53:45Z (6 years ago)

Author:

Petr Manek <petr.manek@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a312d8f

Parents:

d33dc780

Message:

Added memory structure for stream TRB rings. Implemented their initialization. Fixed white space.

File:

• uspace/drv/bus/usb/xhci/hw_struct/context.h (modified) (1 diff)

uspace/drv/bus/usb/xhci/hw_struct/context.h

@@ -169 +169 @@
 #define XHCI_STREAM_SCT_SET(ctx, val) \
         xhci_qword_set_bits(&(ctx).data[0], val, 3, 1)
+#define XHCI_STREAM_DEQ_PTR_SET(ctx, val) \
+        xhci_qword_set_bits(&(ctx).data[0], (val >> 4), 63, 4)
 } __attribute__((packed)) xhci_stream_ctx_t;