Changeset ec443d5 in mainline for kernel/arch/sparc64/src/trap/interrupt.c

Timestamp:

2014-10-20T20:38:13Z (10 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d70ebffe

Parents:

416ef49

Message:

Let most of the sparc64 traps go through exc_dispatch().

• All interrupts (level and vector_trap) now use exc_dispatch().
• Fast MMU traps still don't use it.

File:

• kernel/arch/sparc64/src/trap/interrupt.c (modified) (3 diffs)

kernel/arch/sparc64/src/trap/interrupt.c

@@ -36 +36 @@
 #include <arch/interrupt.h>
 #include <arch/trap/interrupt.h>
+#include <arch/trap/exception.h>
 #include <arch/sparc64.h>
 #include <interrupt.h>
@@ -43 +44 @@
 #include <arch/asm.h>
 #include <arch/barrier.h>
+#include <arch/drivers/tick.h>
 #include <print.h>
 #include <arch.h>
@@ -49 +51 @@
 #include <synch/spinlock.h>
 
-/** Register Interrupt Level Handler.
- *
- * @param n       Interrupt Level (1 - 15).
- * @param name    Short descriptive string.
- * @param handler Handler.
- *
- */
-void interrupt_register(unsigned int n, const char *name, iroutine_t handler)
+void exc_arch_init(void)
 {
-        ASSERT(n >= IVT_FIRST);
-        ASSERT(n <= IVT_ITEMS);
+        exc_register(TT_INSTRUCTION_ACCESS_EXCEPTION,
+            "instruction_access_exception", false,
+            instruction_access_exception);
+        exc_register(TT_INSTRUCTION_ACCESS_ERROR,
+            "instruction_access_error", false,
+            instruction_access_error);
+        exc_register(TT_ILLEGAL_INSTRUCTION,
+            "illegal_instruction", false,
+            illegal_instruction);
+        exc_register(TT_PRIVILEGED_OPCODE,
+            "privileged_opcode", false,
+            privileged_opcode);
+        exc_register(TT_UNIMPLEMENTED_LDD,
+            "unimplemented_LDD", false,
+            unimplemented_LDD);
+        exc_register(TT_UNIMPLEMENTED_STD,
+            "unimplemented_STD", false,
+            unimplemented_STD);
+        exc_register(TT_FP_DISABLED,
+            "fp_disabled", true,
+            fp_disabled);
+        exc_register(TT_FP_EXCEPTION_IEEE_754,
+            "fp_exception_ieee_754", false,
+            fp_exception_ieee_754);
+        exc_register(TT_FP_EXCEPTION_OTHER,
+            "fp_exception_other", false,
+            fp_exception_other);
+        exc_register(TT_TAG_OVERFLOW,
+            "tag_overflow", false,
+            tag_overflow);      
+        exc_register(TT_DIVISION_BY_ZERO,
+            "division_by_zero", false,
+            division_by_zero);
+        exc_register(TT_DATA_ACCESS_EXCEPTION,
+            "data_access_exception", false,
+            data_access_exception);
+        exc_register(TT_DATA_ACCESS_ERROR,
+            "data_access_error", false,
+            data_access_error);
+        exc_register(TT_MEM_ADDRESS_NOT_ALIGNED,
+            "mem_address_not_aligned", false,
+            mem_address_not_aligned);
+        exc_register(TT_LDDF_MEM_ADDRESS_NOT_ALIGNED,
+            "LDDF_mem_address_not_aligned", false,
+            LDDF_mem_address_not_aligned);
+        exc_register(TT_STDF_MEM_ADDRESS_NOT_ALIGNED,
+            "STDF_mem_address_not_aligned", false,
+            STDF_mem_address_not_aligned);
+        exc_register(TT_PRIVILEGED_ACTION,
+            "privileged_action", false,
+            privileged_action);
+        exc_register(TT_LDQF_MEM_ADDRESS_NOT_ALIGNED,
+            "LDQF_mem_address_not_aligned", false,
+            LDQF_mem_address_not_aligned);
+        exc_register(TT_STQF_MEM_ADDRESS_NOT_ALIGNED,
+            "STQF_mem_address_not_aligned", false,
+            STQF_mem_address_not_aligned);
+
+        exc_register(TT_INTERRUPT_LEVEL_14,
+            "interrupt_level_14", true,
+            tick_interrupt);
+
+#ifdef SUN4u 
+        exc_register(TT_INTERRUPT_VECTOR_TRAP,
+            "interrupt_vector_trap", true,
+            interrupt);
+#endif
         
-        exc_register(n - IVT_FIRST, name, true, handler);
 }