Ignore:
Timestamp:
2010-07-25T14:35:05Z (14 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
277cf60
Parents:
24697c3
Message:

Kernel input device for gta02 serial console. Move s3c24xx interrupt controller functionality into a separate C file.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

    r24697c3 rec08286  
    4040#include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
    4141#include <console/chardev.h>
     42#include <console/console.h>
     43#include <ddi/device.h>
    4244#include <arch/asm.h>
    4345#include <mm/slab.h>
    44 #include <console/console.h>
    4546#include <sysinfo/sysinfo.h>
    4647#include <str.h>
    4748
    4849/** S3C24xx UART register offsets */
    49 #define S3C24XX_UTRSTAT         0x10
    50 #define S3C24XX_UTXH            0x20
     50#define S3C24XX_ULCON                   0x00
     51#define S3C24XX_UCON                    0x04
     52#define S3C24XX_UFCON                   0x08
     53#define S3C24XX_UMCON                   0x0c
     54#define S3C24XX_UTRSTAT                 0x10
     55#define S3C24XX_UERSTAT                 0x14
     56#define S3C24XX_UFSTAT                  0x18
     57#define S3C24XX_UMSTAT                  0x1c
     58#define S3C24XX_UTXH                    0x20
     59#define S3C24XX_URXH                    0x24
     60#define S3C24XX_UBRDIV                  0x28
    5161
    52 /* Bits in UTXH register */
    53 #define S3C24XX_UTXH_TX_EMPTY   0x4
    54 
    55 typedef struct {
    56         ioport8_t *base;
    57 } s3c24xx_uart_instance_t;
     62/* Bits in UTRSTAT register */
     63#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
     64#define S3C24XX_UTRSTAT_RDATA           0x1
    5865
    5966static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
     
    6774
    6875        /* Wait for transmitter to be empty. */
    69         while ((pio_read_32(utrstat) & S3C24XX_UTXH_TX_EMPTY) == 0)
     76        while ((pio_read_32(utrstat) & S3C24XX_UTRSTAT_TX_EMPTY) == 0)
    7077                ;
    7178
     
    8693}
    8794
     95static irq_ownership_t s3c24xx_uart_claim(irq_t *irq)
     96{
     97        return IRQ_ACCEPT;
     98}
     99
     100static void s3c24xx_uart_irq_handler(irq_t *irq)
     101{
     102        s3c24xx_uart_instance_t *instance = irq->instance;
     103        ioport32_t *utrstat, *urxh;
     104
     105        utrstat = (ioport32_t *) (instance->base + S3C24XX_UTRSTAT);
     106        urxh = (ioport32_t *) (instance->base + S3C24XX_URXH);
     107
     108        if ((pio_read_32(utrstat) & S3C24XX_UTRSTAT_RDATA) != 0) {
     109                uint32_t data = pio_read_32(urxh);
     110                indev_push_character(instance->indev, data & 0xff);
     111        }
     112}
     113
    88114static outdev_operations_t s3c24xx_uart_ops = {
    89115        .write = s3c24xx_uart_putchar,
     
    91117};
    92118
    93 outdev_t *s3c24xx_uart_init(ioport8_t *base)
     119outdev_t *s3c24xx_uart_init(ioport8_t *base, inr_t inr)
    94120{
    95121        outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
     
    108134
    109135        instance->base = base;
     136        instance->indev = NULL;
     137
     138        /* Initialize IRQ structure. */
     139        irq_initialize(&instance->irq);
     140        instance->irq.devno = device_assign_devno();
     141        instance->irq.inr = inr;
     142        instance->irq.claim = s3c24xx_uart_claim;
     143        instance->irq.handler = s3c24xx_uart_irq_handler;
     144        instance->irq.instance = instance;
     145
     146        /* Disable FIFO */
     147        ioport32_t *ufcon;
     148        ufcon = (ioport32_t *) (instance->base + S3C24XX_UFCON);
     149        pio_write_32(ufcon, pio_read_32(ufcon) & ~0x01);
     150
     151        /* Set RX interrupt to pulse mode */
     152        ioport32_t *ucon;
     153        ucon = (ioport32_t *) (instance->base + S3C24XX_UCON);
     154        pio_write_32(ucon, pio_read_32(ucon) & ~(1 << 8));
    110155
    111156        if (!fb_exported) {
     
    124169}
    125170
     171void s3c24xx_uart_input_wire(s3c24xx_uart_instance_t *instance, indev_t *indev)
     172{
     173        ASSERT(instance);
     174        ASSERT(indev);
     175
     176        instance->indev = indev;
     177        irq_register(&instance->irq);
     178}
     179
    126180/** @}
    127181 */
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