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Changeset e6864f31 in mainline


Ignore:
Timestamp:
2013-02-16T14:55:56Z (9 years ago)
Author:
Maurizio Lombardi <m.lombardi85@…>
Branches:
lfn, master
Children:
92d047e
Parents:
fe6593b7
Message:

remove unused defines

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/include/drivers/am335x/cm_per_regs.h

    rfe6593b7 re6864f31  
    4242
    4343        ioport32_t l4ls_clkstctrl;
    44 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_MASK  0x3
    45 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SHIFT 0
    46 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_FLAG (1 << 8)
    47 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_FLAG (1 << 10)
    48 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_FLAG (1 << 11)
    49 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_FLAG (1 << 13)
    50 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_FLAG (1 << 14)
    51 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_FLAG (1 << 15)
    52 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_FLAG (1 << 16)
    53 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_FLAG (1 << 17)
    54 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO1_GDBCLK_FLAG (1 << 19)
    55 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO2_GDBCLK_FLAG (1 << 20)
    56 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO3_GDBCLK_FLAG (1 << 21)
    57 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_FLAG (1 << 24)
    58 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_FLAG (1 << 25)
    59 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_FLAG (1 << 27)
    60 #define AM335x_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_FLAG (1 << 28)
    61 
    6244        ioport32_t l3ls_clkstctrl;
    63 #define AM335x_CM_PER_L3LS_CLKSTCTRL_CLKTRCTRL_MASK  0x3
    64 #define AM335x_CM_PER_L3LS_CLKSTCTRL_CLKTRCTRL_SHIFT 0
    65 #define AM335x_CM_PER_L3LS_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_FLAG (1 << 3)
    66 
    6745        ioport32_t l4fw_clkstctrl;
    68 #define AM335x_CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_MASK  0x3
    69 #define AM335x_CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SHIFT 0
    70 #define AM335x_CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_FLAG (1 << 8)
    71 
    7246        ioport32_t l3_clkstctrl;
    73 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKTRCTRL_MASK  0x3
    74 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SHIFT 0
    75 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_FLAG (1 << 2)
    76 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_FLAG  (1 << 3)
    77 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_FLAG   (1 << 4)
    78 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_FLAG (1 << 6)
    79 #define AM335x_CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_FLAG (1 << 7)
    8047
    8148        ioport32_t const pad0;
    8249
    8350        ioport32_t cpgmac0_clkctrl;
    84 #define AM335x_CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_MASK  0x3
    85 #define AM335x_CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_SHIFT 0
    86 #define AM335x_CM_PER_CPGMAC0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    87 #define AM335x_CM_PER_CPGMAC0_CLKCTRL_IDLEST_SHIFT     16
    88 #define AM335x_CM_PER_CPGMAC0_CLKCTRL_STBYST_FLAG      (1 << 18)
    89 
    9051        ioport32_t lcdc_clkctrl;
    91 #define AM335x_CM_PER_LCDC_CLKCTRL_MODULEMODE_MASK  0x3
    92 #define AM335x_CM_PER_LCDC_CLKCTRL_MODULEMODE_SHIFT 0
    93 #define AM335x_CM_PER_LCDC_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    94 #define AM335x_CM_PER_LCDC_CLKCTRL_IDLEST_SHIFT     16
    95 #define AM335x_CM_PER_LCDC_CLKCTRL_STBYST_FLAG      (1 << 18)
    96 
    9752        ioport32_t usb0_clkctrl;
    98 #define AM335x_CM_PER_USB0_CLKCTRL_MODULEMODE_MASK  0x3
    99 #define AM335x_CM_PER_USB0_CLKCTRL_MODULEMODE_SHIFT 0
    100 #define AM335x_CM_PER_USB0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    101 #define AM335x_CM_PER_USB0_CLKCTRL_IDLEST_SHIFT     16
    102 #define AM335x_CM_PER_USB0_CLKCTRL_STBYST_FLAG      (1 << 18)
    10353
    10454        ioport32_t const pad1;
    10555
    10656        ioport32_t tptc0_clkctrl;
    107 #define AM335x_CM_PER_TPTC0_CLKCTRL_MODULEMODE_MASK  0x3
    108 #define AM335x_CM_PER_TPTC0_CLKCTRL_MODULEMODE_SHIFT 0
    109 #define AM335x_CM_PER_TPTC0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    110 #define AM335x_CM_PER_TPTC0_CLKCTRL_IDLEST_SHIFT     16
    111 #define AM335x_CM_PER_TPTC0_CLKCTRL_STBYST_FLAG      (1 << 18)
    112 
    11357        ioport32_t emif_clkctrl;
    114 #define AM335x_CM_PER_EMIF_CLKCTRL_MODULEMODE_MASK  0x3
    115 #define AM335x_CM_PER_EMIF_CLKCTRL_MODULEMODE_SHIFT 0
    116 #define AM335x_CM_PER_EMIF_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    117 #define AM335x_CM_PER_EMIF_CLKCTRL_IDLEST_SHIFT     16
    118 
    11958        ioport32_t ocmcram_clkctrl;
    120 #define AM335x_CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_MASK  0x3
    121 #define AM335x_CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_SHIFT 0
    122 #define AM335x_CM_PER_OCMCRAM_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    123 #define AM335x_CM_PER_OCMCRAM_CLKCTRL_IDLEST_SHIFT     16
    124 
    12559        ioport32_t gpmc_clkctrl;
    126 #define AM335x_CM_PER_GPMC_CLKCTRL_MODULEMODE_MASK  0x3
    127 #define AM335x_CM_PER_GPMC_CLKCTRL_MODULEMODE_SHIFT 0
    128 #define AM335x_CM_PER_GPMC_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    129 #define AM335x_CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT     16
    130 
    13160        ioport32_t mcasp0_clkctrl;
    132 #define AM335x_CM_PER_MCASP0_CLKCTRL_MODULEMODE_MASK  0x3
    133 #define AM335x_CM_PER_MCASP0_CLKCTRL_MODULEMODE_SHIFT 0
    134 #define AM335x_CM_PER_MCASP0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    135 #define AM335x_CM_PER_MCASP0_CLKCTRL_IDLEST_SHIFT     16
    136 
    13761        ioport32_t uart5_clkctrl;
    138 #define AM335x_CM_PER_UART5_CLKCTRL_MODULEMODE_MASK  0x3
    139 #define AM335x_CM_PER_UART5_CLKCTRL_MODULEMODE_SHIFT 0
    140 #define AM335x_CM_PER_UART5_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    141 #define AM335x_CM_PER_UART5_CLKCTRL_IDLEST_SHIFT     16
    142 
    14362        ioport32_t mmc0_clkctrl;
    144 #define AM335x_CM_PER_MMC0_CLKCTRL_MODULEMODE_MASK  0x3
    145 #define AM335x_CM_PER_MMC0_CLKCTRL_MODULEMODE_SHIFT 0
    146 #define AM335x_CM_PER_MMC0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    147 #define AM335x_CM_PER_MMC0_CLKCTRL_IDLEST_SHIFT     16
    148 
    14963        ioport32_t elm_clkctrl;
    150 #define AM335x_CM_PER_ELM_CLKCTRL_MODULEMODE_MASK  0x3
    151 #define AM335x_CM_PER_ELM_CLKCTRL_MODULEMODE_SHIFT 0
    152 #define AM335x_CM_PER_ELM_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    153 #define AM335x_CM_PER_ELM_CLKCTRL_IDLEST_SHIFT     16
    154 
    15564        ioport32_t i2c2_clkctrl;
    156 #define AM335x_CM_PER_I2C2_CLKCTRL_MODULEMODE_MASK  0x3
    157 #define AM335x_CM_PER_I2C2_CLKCTRL_MODULEMODE_SHIFT 0
    158 #define AM335x_CM_PER_I2C2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    159 #define AM335x_CM_PER_I2C2_CLKCTRL_IDLEST_SHIFT     16
    160 
    16165        ioport32_t i2c1_clkctrl;
    162 #define AM335x_CM_PER_I2C1_CLKCTRL_MODULEMODE_MASK  0x3
    163 #define AM335x_CM_PER_I2C1_CLKCTRL_MODULEMODE_SHIFT 0
    164 #define AM335x_CM_PER_I2C1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    165 #define AM335x_CM_PER_I2C1_CLKCTRL_IDLEST_SHIFT     16
    166 
    16766        ioport32_t spi0_clkctrl;
    168 #define AM335x_CM_PER_SPI0_CLKCTRL_MODULEMODE_MASK  0x3
    169 #define AM335x_CM_PER_SPI0_CLKCTRL_MODULEMODE_SHIFT 0
    170 #define AM335x_CM_PER_SPI0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    171 #define AM335x_CM_PER_SPI0_CLKCTRL_IDLEST_SHIFT     16
    172 
    17367        ioport32_t spi1_clkctrl;
    174 #define AM335x_CM_PER_SPI1_CLKCTRL_MODULEMODE_MASK  0x3
    175 #define AM335x_CM_PER_SPI1_CLKCTRL_MODULEMODE_SHIFT 0
    176 #define AM335x_CM_PER_SPI1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    177 #define AM335x_CM_PER_SPI1_CLKCTRL_IDLEST_SHIFT     16
    17868
    17969        ioport32_t const pad2[3];
    18070
    18171        ioport32_t l4ls_clkctrl;
    182 #define AM335x_CM_PER_L4LS_CLKCTRL_MODULEMODE_MASK  0x3
    183 #define AM335x_CM_PER_L4LS_CLKCTRL_MODULEMODE_SHIFT 0
    184 #define AM335x_CM_PER_L4LS_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    185 #define AM335x_CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT     16
    186 
    18772        ioport32_t l4fw_clkctrl;
    188 #define AM335x_CM_PER_L4FW_CLKCTRL_MODULEMODE_MASK  0x3
    189 #define AM335x_CM_PER_L4FW_CLKCTRL_MODULEMODE_SHIFT 0
    190 #define AM335x_CM_PER_L4FW_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    191 #define AM335x_CM_PER_L4FW_CLKCTRL_IDLEST_SHIFT     16
    192 
    19373        ioport32_t mcasp1_clkctrl;
    194 #define AM335x_CM_PER_MCASP1_CLKCTRL_MODULEMODE_MASK  0x3
    195 #define AM335x_CM_PER_MCASP1_CLKCTRL_MODULEMODE_SHIFT 0
    196 #define AM335x_CM_PER_MCASP1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    197 #define AM335x_CM_PER_MCASP1_CLKCTRL_IDLEST_SHIFT     16
    198 
    19974        ioport32_t uart1_clkctrl;
    200 #define AM335x_CM_PER_UART1_CLKCTRL_MODULEMODE_MASK  0x3
    201 #define AM335x_CM_PER_UART1_CLKCTRL_MODULEMODE_SHIFT 0
    202 #define AM335x_CM_PER_UART1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    203 #define AM335x_CM_PER_UART1_CLKCTRL_IDLEST_SHIFT     16
    204 
    20575        ioport32_t uart2_clkctrl;
    206 #define AM335x_CM_PER_UART2_CLKCTRL_MODULEMODE_MASK  0x3
    207 #define AM335x_CM_PER_UART2_CLKCTRL_MODULEMODE_SHIFT 0
    208 #define AM335x_CM_PER_UART2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    209 #define AM335x_CM_PER_UART2_CLKCTRL_IDLEST_SHIFT     16
    210 
    21176        ioport32_t uart3_clkctrl;
    212 #define AM335x_CM_PER_UART3_CLKCTRL_MODULEMODE_MASK  0x3
    213 #define AM335x_CM_PER_UART3_CLKCTRL_MODULEMODE_SHIFT 0
    214 #define AM335x_CM_PER_UART3_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    215 #define AM335x_CM_PER_UART3_CLKCTRL_IDLEST_SHIFT     16
    216 
    21777        ioport32_t uart4_clkctrl;
    218 #define AM335x_CM_PER_UART4_CLKCTRL_MODULEMODE_MASK  0x3
    219 #define AM335x_CM_PER_UART4_CLKCTRL_MODULEMODE_SHIFT 0
    220 #define AM335x_CM_PER_UART4_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    221 #define AM335x_CM_PER_UART4_CLKCTRL_IDLEST_SHIFT     16
    222 
    22378        ioport32_t timer7_clkctrl;
    224 #define AM335x_CM_PER_TIMER7_CLKCTRL_MODULEMODE_MASK  0x3
    225 #define AM335x_CM_PER_TIMER7_CLKCTRL_MODULEMODE_SHIFT 0
    226 #define AM335x_CM_PER_TIMER7_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    227 #define AM335x_CM_PER_TIMER7_CLKCTRL_IDLEST_SHIFT     16
    228 
    22979        ioport32_t timer2_clkctrl;
    230 #define AM335x_CM_PER_TIMER2_CLKCTRL_MODULEMODE_MASK  0x3
    231 #define AM335x_CM_PER_TIMER2_CLKCTRL_MODULEMODE_SHIFT 0
    232 #define AM335x_CM_PER_TIMER2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    233 #define AM335x_CM_PER_TIMER2_CLKCTRL_IDLEST_SHIFT     16
    234 
    23580        ioport32_t timer3_clkctrl;
    236 #define AM335x_CM_PER_TIMER3_CLKCTRL_MODULEMODE_MASK  0x3
    237 #define AM335x_CM_PER_TIMER3_CLKCTRL_MODULEMODE_SHIFT 0
    238 #define AM335x_CM_PER_TIMER3_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    239 #define AM335x_CM_PER_TIMER3_CLKCTRL_IDLEST_SHIFT     16
    240 
    24181        ioport32_t timer4_clkctrl;
    242 #define AM335x_CM_PER_TIMER4_CLKCTRL_MODULEMODE_MASK  0x3
    243 #define AM335x_CM_PER_TIMER4_CLKCTRL_MODULEMODE_SHIFT 0
    244 #define AM335x_CM_PER_TIMER4_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    245 #define AM335x_CM_PER_TIMER4_CLKCTRL_IDLEST_SHIFT     16
    24682
    24783        ioport32_t const pad3[8];
    24884
    24985        ioport32_t gpio1_clkctrl;
    250 #define AM335x_CM_PER_GPIO1_CLKCTRL_MODULEMODE_MASK  0x3
    251 #define AM335x_CM_PER_GPIO1_CLKCTRL_MODULEMODE_SHIFT 0
    252 #define AM335x_CM_PER_GPIO1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    253 #define AM335x_CM_PER_GPIO1_CLKCTRL_IDLEST_SHIFT     16
    254 #define AM335x_CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_FLAG   (1 << 18)
    255 
    25686        ioport32_t gpio2_clkctrl;
    257 #define AM335x_CM_PER_GPIO2_CLKCTRL_MODULEMODE_MASK  0x3
    258 #define AM335x_CM_PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT 0
    259 #define AM335x_CM_PER_GPIO2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    260 #define AM335x_CM_PER_GPIO2_CLKCTRL_IDLEST_SHIFT     16
    261 #define AM335x_CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_FLAG   (1 << 18)
    262 
    26387        ioport32_t gpio3_clkctrl;
    264 #define AM335x_CM_PER_GPIO3_CLKCTRL_MODULEMODE_MASK  0x3
    265 #define AM335x_CM_PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT 0
    266 #define AM335x_CM_PER_GPIO3_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    267 #define AM335x_CM_PER_GPIO3_CLKCTRL_IDLEST_SHIFT     16
    268 #define AM335x_CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_FLAG   (1 << 18)
    26988
    27089        ioport32_t const pad4;
    27190
    27291        ioport32_t tpcc_clkctrl;
    273 #define AM335x_CM_PER_TPCC_CLKCTRL_MODULEMODE_MASK  0x3
    274 #define AM335x_CM_PER_TPCC_CLKCTRL_MODULEMODE_SHIFT 0
    275 #define AM335x_CM_PER_TPCC_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    276 #define AM335x_CM_PER_TPCC_CLKCTRL_IDLEST_SHIFT     16
    277 
    27892        ioport32_t dcan0_clkctrl;
    279 #define AM335x_CM_PER_DCAN0_CLKCTRL_MODULEMODE_MASK  0x3
    280 #define AM335x_CM_PER_DCAN0_CLKCTRL_MODULEMODE_SHIFT 0
    281 #define AM335x_CM_PER_DCAN0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    282 #define AM335x_CM_PER_DCAN0_CLKCTRL_IDLEST_SHIFT     16
    283 
    28493        ioport32_t dcan1_clkctrl;
    285 #define AM335x_CM_PER_DCAN1_CLKCTRL_MODULEMODE_MASK  0x3
    286 #define AM335x_CM_PER_DCAN1_CLKCTRL_MODULEMODE_SHIFT 0
    287 #define AM335x_CM_PER_DCAN1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    288 #define AM335x_CM_PER_DCAN1_CLKCTRL_IDLEST_SHIFT     16
    289 
    29094        ioport32_t epwmss1_clkctrl;
    291 #define AM335x_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_MASK  0x3
    292 #define AM335x_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_SHIFT 0
    293 #define AM335x_CM_PER_EPWMSS1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    294 #define AM335x_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT     16
    295 
    29695        ioport32_t emiffw_clkctrl;
    297 #define AM335x_CM_PER_EMIFFW_CLKCTRL_MODULEMODE_MASK  0x3
    298 #define AM335x_CM_PER_EMIFFW_CLKCTRL_MODULEMODE_SHIFT 0
    299 #define AM335x_CM_PER_EMIFFW_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    300 #define AM335x_CM_PER_EMIFFW_CLKCTRL_IDLEST_SHIFT     16
    301 
    30296        ioport32_t epwmss0_clkctrl;
    303 #define AM335x_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_MASK  0x3
    304 #define AM335x_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_SHIFT 0
    305 #define AM335x_CM_PER_EPWMSS0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    306 #define AM335x_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT     16
    307 
    30897        ioport32_t epwmss2_clkctrl;
    309 #define AM335x_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_MASK  0x3
    310 #define AM335x_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_SHIFT 0
    311 #define AM335x_CM_PER_EPWMSS2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    312 #define AM335x_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT     16
    313 
    31498        ioport32_t l3instr_clkctrl;
    315 #define AM335x_CM_PER_L3INSTR_CLKCTRL_MODULEMODE_MASK  0x3
    316 #define AM335x_CM_PER_L3INSTR_CLKCTRL_MODULEMODE_SHIFT 0
    317 #define AM335x_CM_PER_L3INSTR_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    318 #define AM335x_CM_PER_L3INSTR_CLKCTRL_IDLEST_SHIFT     16
    319 
    32099        ioport32_t l3_clkctrl;
    321 #define AM335x_CM_PER_L3_CLKCTRL_MODULEMODE_MASK  0x3
    322 #define AM335x_CM_PER_L3_CLKCTRL_MODULEMODE_SHIFT 0
    323 #define AM335x_CM_PER_L3_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    324 #define AM335x_CM_PER_L3_CLKCTRL_IDLEST_SHIFT     16
    325 
    326100        ioport32_t ieee5000_clkctrl;
    327 #define AM335x_CM_PER_IEEE5000_CLKCTRL_MODULEMODE_MASK  0x3
    328 #define AM335x_CM_PER_IEEE5000_CLKCTRL_MODULEMODE_SHIFT 0
    329 #define AM335x_CM_PER_IEEE5000_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    330 #define AM335x_CM_PER_IEEE5000_CLKCTRL_IDLEST_SHIFT     16
    331 #define AM335x_CM_PER_IEEE5000_CLKCTRL_STBYST_FLAG      (1 << 18)
    332 
    333101        ioport32_t pruicss_clkctrl;
    334 #define AM335x_CM_PER_PRUICSS_CLKCTRL_MODULEMODE_MASK  0x3
    335 #define AM335x_CM_PER_PRUICSS_CLKCTRL_MODULEMODE_SHIFT 0
    336 #define AM335x_CM_PER_PRUICSS_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    337 #define AM335x_CM_PER_PRUICSS_CLKCTRL_IDLEST_SHIFT     16
    338 #define AM335x_CM_PER_PRUICSS_CLKCTRL_STBYST_FLAG      (1 << 18)
    339 
    340102        ioport32_t timer5_clkctrl;
    341 #define AM335x_CM_PER_TIMER5_CLKCTRL_MODULEMODE_MASK  0x3
    342 #define AM335x_CM_PER_TIMER5_CLKCTRL_MODULEMODE_SHIFT 0
    343 #define AM335x_CM_PER_TIMER5_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    344 #define AM335x_CM_PER_TIMER5_CLKCTRL_IDLEST_SHIFT     16
    345 
    346103        ioport32_t timer6_clkctrl;
    347 #define AM335x_CM_PER_TIMER6_CLKCTRL_MODULEMODE_MASK  0x3
    348 #define AM335x_CM_PER_TIMER6_CLKCTRL_MODULEMODE_SHIFT 0
    349 #define AM335x_CM_PER_TIMER6_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    350 #define AM335x_CM_PER_TIMER6_CLKCTRL_IDLEST_SHIFT     16
    351 
    352104        ioport32_t mmc1_clkctrl;
    353 #define AM335x_CM_PER_MMC1_CLKCTRL_MODULEMODE_MASK  0x3
    354 #define AM335x_CM_PER_MMC1_CLKCTRL_MODULEMODE_SHIFT 0
    355 #define AM335x_CM_PER_MMC1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    356 #define AM335x_CM_PER_MMC1_CLKCTRL_IDLEST_SHIFT     16
    357 
    358105        ioport32_t mmc2_clkctrl;
    359 #define AM335x_CM_PER_MMC2_CLKCTRL_MODULEMODE_MASK  0x3
    360 #define AM335x_CM_PER_MMC2_CLKCTRL_MODULEMODE_SHIFT 0
    361 #define AM335x_CM_PER_MMC2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    362 #define AM335x_CM_PER_MMC2_CLKCTRL_IDLEST_SHIFT     16
    363 
    364106        ioport32_t tptc1_clkctrl;
    365 #define AM335x_CM_PER_TPTC1_CLKCTRL_MODULEMODE_MASK  0x3
    366 #define AM335x_CM_PER_TPTC1_CLKCTRL_MODULEMODE_SHIFT 0
    367 #define AM335x_CM_PER_TPTC1_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    368 #define AM335x_CM_PER_TPTC1_CLKCTRL_IDLEST_SHIFT     16
    369 #define AM335x_CM_PER_TPTC1_CLKCTRL_STBYST_FLAG      (1 << 18)
    370 
    371107        ioport32_t tptc2_clkctrl;
    372 #define AM335x_CM_PER_TPTC2_CLKCTRL_MODULEMODE_MASK  0x3
    373 #define AM335x_CM_PER_TPTC2_CLKCTRL_MODULEMODE_SHIFT 0
    374 #define AM335x_CM_PER_TPTC2_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    375 #define AM335x_CM_PER_TPTC2_CLKCTRL_IDLEST_SHIFT     16
    376 #define AM335x_CM_PER_TPTC2_CLKCTRL_STBYST_FLAG      (1 << 18)
    377108
    378109        ioport32_t const pad5[2];
    379110
    380111        ioport32_t spinlock_clkctrl;
    381 #define AM335x_CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_MASK  0x3
    382 #define AM335x_CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_SHIFT 0
    383 #define AM335x_CM_PER_SPINLOCK_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    384 #define AM335x_CM_PER_SPINLOCK_CLKCTRL_IDLEST_SHIFT     16
    385 
    386112        ioport32_t mailbox0_clkctrl;
    387 #define AM335x_CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_MASK  0x3
    388 #define AM335x_CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_SHIFT 0
    389 #define AM335x_CM_PER_MAILBOX0_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    390 #define AM335x_CM_PER_MAILBOX0_CLKCTRL_IDLEST_SHIFT     16
    391113
    392114        ioport32_t const pad6[2];
    393115
    394116        ioport32_t l4hs_clkstctrl;
    395 #define AM335x_CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_MASK     0x3
    396 #define AM335x_CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SHIFT    0
    397 #define AM335x_CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_FLAG        (1 << 3)
    398 #define AM335x_CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_FLAG (1 << 4)
    399 #define AM335x_CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_FLAG  (1 << 5)
    400 #define AM335x_CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_FLAG   (1 << 6)
    401 
    402117        ioport32_t l4hs_clkctrl;
    403 #define AM335x_CM_PER_L4HS_CLKCTRL_MODULEMODE_MASK  0x3
    404 #define AM335x_CM_PER_L4HS_CLKCTRL_MODULEMODE_SHIFT 0
    405 #define AM335x_CM_PER_L4HS_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    406 #define AM335x_CM_PER_L4HS_CLKCTRL_IDLEST_SHIFT     16
    407118
    408119        ioport32_t const pad7[2];
    409120
    410121        ioport32_t ocpwp_l3_clkstctrl;
    411 #define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_MASK     0x3
    412 #define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SHIFT    0
    413 #define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_FLAG (1 << 4)
    414 #define AM335x_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_FLAG (1 << 5)
    415 
    416122        ioport32_t ocpwp_clkctrl;
    417 #define AM335x_CM_PER_OCPWP_CLKCTRL_MODULEMODE_MASK  0x3
    418 #define AM335x_CM_PER_OCPWP_CLKCTRL_MODULEMODE_SHIFT 0
    419 #define AM335x_CM_PER_OCPWP_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    420 #define AM335x_CM_PER_OCPWP_CLKCTRL_IDLEST_SHIFT     16
    421 #define AM335x_CM_PER_OCPWP_CLKCTRL_STBYST_FLAG      (1 << 18)
    422123
    423124        ioport32_t const pad8[3];
    424125
    425126        ioport32_t pruicss_clkstctrl;
    426 #define AM335x_CM_PER_PRUICSS_CLKSTCTRL_CLKTRCTRL_MASK     0x3
    427 #define AM335x_CM_PER_PRUICSS_CLKSTCTRL_CLKTRCTRL_SHIFT    0
    428 #define AM335x_CM_PER_PRUICSS_CLKSTCTRL_CLKACTIVITY_PRUICSS_OCP_FLAG  (1 << 4)
    429 #define AM335x_CM_PER_PRUICSS_CLKSTCTRL_CLKACTIVITY_PRUICSS_IEP_FLAG  (1 << 5)
    430 #define AM335x_CM_PER_PRUICSS_CLKSTCTRL_CLKACTIVITY_PRUICSS_UART_FLAG (1 << 5)
    431 
    432127        ioport32_t cpsw_clkstctrl;
    433 #define AM335x_CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_MASK     0x3
    434 #define AM335x_CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SHIFT    0
    435 #define AM335x_CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_FLAG  (1 << 4)
    436 
    437128        ioport32_t lcdc_clkstctrl;
    438 #define AM335x_CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_MASK     0x3
    439 #define AM335x_CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SHIFT    0
    440 #define AM335x_CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_FLAG  (1 << 4)
    441 #define AM335x_CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_FLAG  (1 << 5)
    442 
    443129        ioport32_t clkdiv32_clkctrl;
    444 #define AM335x_CM_PER_CLKDIV32_CLKCTRL_MODULEMODE_MASK  0x3
    445 #define AM335x_CM_PER_CLKDIV32_CLKCTRL_MODULEMODE_SHIFT 0
    446 #define AM335x_CM_PER_CLKDIV32_CLKCTRL_IDLEST_MASK      (0x3 << 16)
    447 #define AM335x_CM_PER_CLKDIV32_CLKCTRL_IDLEST_SHIFT     16
    448 
    449130        ioport32_t clk24mhz_clkstctrl;
    450 #define AM335x_CM_PER_CLK24MHZ_CLKSTCTRL_CLKTRCTRL_MASK     0x3
    451 #define AM335x_CM_PER_CLK24MHZ_CLKSTCTRL_CLKTRCTRL_SHIFT    0
    452 #define AM335x_CM_PER_CLK24MHZ_CLKSTCTRL_CLKACTIVITY_CLK24MHZ_FLAG  (1 << 4)
    453 
    454131} am335x_cm_per_regs_t;
    455132
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