Changeset e4f8c77 in mainline for kernel/arch/mips32/src/mm/tlb.c
- Timestamp:
- 2011-07-13T22:39:18Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e6910c8
- Parents:
- 5974661 (diff), 8ecef91 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/mips32/src/mm/tlb.c
r5974661 re4f8c77 73 73 tlbwi(); 74 74 } 75 75 76 76 /* 77 77 * The kernel is going to make use of some wired … … 386 386 ASSERT(pte->w || access != PF_ACCESS_WRITE); 387 387 return pte; 388 break;389 388 case AS_PF_DEFER: 390 389 *pfrc = AS_PF_DEFER; 391 390 return NULL; 392 break;393 391 case AS_PF_FAULT: 394 392 *pfrc = AS_PF_FAULT; 395 393 return NULL; 396 break;397 394 default: 398 395 panic("Unexpected rc (%d).", rc);
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