Changeset e2b73d4f in mainline for uspace/srv/hw/char/i8042/i8042.c
- Timestamp:
- 2010-03-21T09:25:29Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade
- Children:
- 19f857a
- Parents:
- facebd56 (diff), 4e9aaf5 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - File:
-
- 1 edited
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uspace/srv/hw/char/i8042/i8042.c
rfacebd56 re2b73d4f 68 68 #define i8042_KBD_TRANSLATE 0x40 69 69 70 /* Mouse constants */71 #define MOUSE_OUT_INIT 0xf472 #define MOUSE_ACK 0xfa73 70 74 71 enum { … … 177 174 async_set_interrupt_received(i8042_irq_handler); 178 175 179 /* Disable kbd, enable mouse */ 176 /* Disable kbd and aux */ 177 wait_ready(); 180 178 pio_write_8(&i8042->status, i8042_CMD_WRITE_CMDB); 181 179 wait_ready(); 182 pio_write_8(&i8042->status, i8042_CMD_WRITE_CMDB); 183 wait_ready(); 184 pio_write_8(&i8042->data, i8042_KBD_DISABLE); 185 wait_ready(); 180 pio_write_8(&i8042->data, i8042_KBD_DISABLE | i8042_AUX_DISABLE); 186 181 187 182 /* Flush all current IO */ 188 183 while (pio_read_8(&i8042->status) & i8042_OUTPUT_FULL) 189 184 (void) pio_read_8(&i8042->data); 190 191 i8042_port_write(DEVID_AUX, MOUSE_OUT_INIT);192 185 193 186 i8042_kbd.cmds[0].addr = (void *) &((i8042_t *) i8042_kernel)->status; … … 195 188 ipc_register_irq(sysinfo_value("i8042.inr_a"), device_assign_devno(), 0, &i8042_kbd); 196 189 ipc_register_irq(sysinfo_value("i8042.inr_b"), device_assign_devno(), 0, &i8042_kbd); 197 190 printf("i8042: registered for interrupts %d and %d\n", 191 sysinfo_value("i8042.inr_a"), sysinfo_value("i8042.inr_b")); 192 193 wait_ready(); 198 194 pio_write_8(&i8042->status, i8042_CMD_WRITE_CMDB); 199 195 wait_ready(); 200 196 pio_write_8(&i8042->data, i8042_KBD_IE | i8042_KBD_TRANSLATE | 201 197 i8042_AUX_IE); 202 wait_ready();203 198 204 199 return 0; … … 271 266 { 272 267 if (devid == DEVID_AUX) { 268 wait_ready(); 273 269 pio_write_8(&i8042->status, i8042_CMD_WRITE_AUX); 274 wait_ready();275 }270 } 271 wait_ready(); 276 272 pio_write_8(&i8042->data, data); 277 wait_ready();278 273 } 279 274
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