Changeset e25eca80 in mainline


Ignore:
Timestamp:
2008-06-13T20:36:38Z (16 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d5087aa
Parents:
80dabb8d
Message:

Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented.

Location:
kernel/arch
Files:
1 added
9 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/barrier.h

    r80dabb8d re25eca80  
    4747#define write_barrier()         asm volatile ("" ::: "memory")
    4848
     49#define smc_coherence(a)
     50
    4951#endif
    5052

  • kernel/arch/ia32/include/barrier.h

    r80dabb8d re25eca80  
    8585#endif
    8686
     87/*
     88 * On ia32, the hardware takes care about instruction and data cache coherence,
     89 * even on SMP systems.  We issue a write barrier to be sure that writes
     90 * queueing in the store buffer drain to the memory (even though it would be
     91 * sufficient for them to drain to the D-cache).
     92 */
     93#define smc_coherence(a)                write_barrier()
     94
    8795#endif
    8896

  • kernel/arch/ia64/include/barrier.h

    r80dabb8d re25eca80  
    4646#define write_barrier()         memory_barrier()
    4747
    48 #define srlz_i()                asm volatile (";; srlz.i ;;\n" ::: "memory")
    49 #define srlz_d()                asm volatile (";; srlz.d\n" ::: "memory")
     48#define srlz_i()                \
     49        asm volatile (";; srlz.i ;;\n" ::: "memory")
     50#define srlz_d()                \
     51        asm volatile (";; srlz.d\n" ::: "memory")
     52
     53#define fc_i(a)                 \
     54        asm volatile ("fc.i %0\n" : "r" ((a)) :: "memory") 
     55#define sync_i()                \
     56        asm volatile (";; sync.i\n" ::: "memory")
     57
     58#define smc_coherence(a)        \
     59{                               \
     60        fc_i((a));              \
     61        sync_i();               \
     62        srlz_i();               \
     63}
    5064
    5165#endif

  • kernel/arch/mips32/include/barrier.h

    r80dabb8d re25eca80  
    4646#define write_barrier()         asm volatile ("" ::: "memory")
    4747
     48#define smc_coherence(a)
     49
    4850#endif
    4951

  • kernel/arch/ppc32/include/barrier.h

    r80dabb8d re25eca80  
    4343#define write_barrier() asm volatile ("eieio" ::: "memory")
    4444
     45#define smc_coherence(a)
     46
    4547#endif
    4648

  • kernel/arch/ppc64/include/barrier.h

    r80dabb8d re25eca80  
    3939#define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
    4040
    41 #define memory_barrier() asm volatile ("sync" ::: "memory")
    42 #define read_barrier() asm volatile ("sync" ::: "memory")
    43 #define write_barrier() asm volatile ("eieio" ::: "memory")
     41#define memory_barrier()        asm volatile ("sync" ::: "memory")
     42#define read_barrier()          asm volatile ("sync" ::: "memory")
     43#define write_barrier()         asm volatile ("eieio" ::: "memory")
     44
     45#define smc_coherence(a)
    4446
    4547#endif

  • kernel/arch/sparc64/include/barrier.h

    r80dabb8d re25eca80  
    5858        asm volatile ("membar #StoreStore\n" ::: "memory")
    5959
     60static inline void flush(uintptr_t addr)
     61{
     62        asm volatile ("flush %0\n" :: "r" (addr) : "memory");
     63}
     64
    6065/** Flush Instruction Memory instruction. */
    61 static inline void flush(void)
     66static inline void flush_blind(void)
    6267{
    6368        /*
    … …  
    8085}
    8186
     87#define smc_coherence(a)        \
     88{                               \
     89        write_barrier();        \
     90        flush((a));             \
     91}
     92
    8293#endif
    8394

  • kernel/arch/sparc64/include/mm/tlb.h

    r80dabb8d re25eca80  
    161161{
    162162        asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
    163         flush();
     163        flush_blind();
    164164}
    165165
    … …  
    180180{
    181181        asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
    182         flush();
     182        flush_blind();
    183183}
    184184
    … …  
    210210        reg.tlb_entry = entry;
    211211        asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
    212         flush();
     212        flush_blind();
    213213}
    214214
    … …  
    280280{
    281281        asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
    282         flush();
     282        flush_blind();
    283283}
    284284
    … …  
    319319{
    320320        asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
    321         flush();
     321        flush_blind();
    322322}
    323323
    … …  
    348348{
    349349        asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
    350         flush();
     350        flush_blind();
    351351}
    352352
    … …  
    401401                                                         * address within the
    402402                                                         * ASI */
    403         flush();
     403        flush_blind();
    404404}
    405405

  • kernel/arch/sparc64/src/mm/cache.S

    r80dabb8d re25eca80  
    2828
    2929#include <arch/arch.h>
    30 
    31 #define DCACHE_SIZE             (16 * 1024)
    32 #define DCACHE_LINE_SIZE        32     
     30#include <arch/mm/cache_spec.h>
    3331
    3432#define DCACHE_TAG_SHIFT        2
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