Changeset de96d3b in mainline for kernel/arch/amd64/include/arch/mm/page.h
- Timestamp:
- 2024-01-03T16:54:15Z (4 months ago)
- Branches:
- master, topic/simplify-dev-export
- Children:
- 00e6288, 25e1490
- Parents:
- 7130754
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2024-01-01 04:12:52)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2024-01-03 16:54:15)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/include/arch/mm/page.h
r7130754 rde96d3b 192 192 unsigned int accessed : 1; 193 193 unsigned int dirty : 1; 194 unsigned int unused: 1;194 unsigned int pat : 1; 195 195 unsigned int global : 1; 196 196 unsigned int soft_valid : 1; /**< Valid content even if present bit is cleared. */ … … 211 211 p->writeable << PAGE_WRITE_SHIFT | 212 212 (!p->no_execute) << PAGE_EXEC_SHIFT | 213 p->global << PAGE_GLOBAL_SHIFT); 213 p->global << PAGE_GLOBAL_SHIFT | 214 p->page_write_through << PAGE_WRITE_COMBINE_SHIFT); 214 215 } 215 216 … … 225 226 pte_t *p = &pt[i]; 226 227 227 p->page_cache_disable = !(flags & PAGE_CACHEABLE);228 228 p->present = !(flags & PAGE_NOT_PRESENT); 229 229 p->uaccessible = (flags & PAGE_USER) != 0; … … 232 232 p->global = (flags & PAGE_GLOBAL) != 0; 233 233 234 if (flags & PAGE_WRITE_COMBINE) { 235 /* We have mapped PCD+PWT bits to write-combine mode via PAT MSR. */ 236 /* (If PAT is unsupported, it will default to uncached.) */ 237 p->page_cache_disable = 1; 238 p->page_write_through = 1; 239 } else { 240 p->page_cache_disable = !(flags & PAGE_CACHEABLE); 241 p->page_write_through = 0; 242 } 243 234 244 /* 235 245 * Ensure that there is at least one bit set even if the present bit is cleared.
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