Fork us on GitHub Follow us on Facebook Follow us on Twitter

Changeset db6e419 in mainline for kernel/arch/mips32/include/cp0.h


Ignore:
Timestamp:
2011-08-16T18:53:00Z (10 years ago)
Author:
Petr Koupy <petr.koupy@…>
Branches:
lfn, master
Children:
49160c4
Parents:
e0e922d (diff), 45058baa (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/mips32/include/cp0.h

    re0e922d rdb6e419  
    3636#define KERN_mips32_CP0_H_
    3737
    38 #ifdef KERNEL
    39 #include <typedefs.h>
    40 #else
    41 #include <sys/types.h>
    42 #endif
    43 
    4438#define cp0_status_ie_enabled_bit     (1 << 0)
    4539#define cp0_status_exl_exception_bit  (1 << 1)
     
    4943#define cp0_status_fpu_bit            (1 << 29)
    5044
    51 #define cp0_status_im_shift             8
    52 #define cp0_status_im_mask              0xff00
     45#define cp0_status_im_shift  8
     46#define cp0_status_im_mask   0xff00
    5347
    54 #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
    55 #define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
     48#define cp0_cause_excno(cause)   ((cause >> 2) & 0x1f)
     49#define cp0_cause_coperr(cause)  ((cause >> 28) & 0x3)
    5650
    57 #define fpu_cop_id 1
     51#define fpu_cop_id  1
    5852
    5953/*
    6054 * Magic value for use in msim.
    6155 */
    62 #define cp0_compare_value               100000
     56#define cp0_compare_value  100000
    6357
    64 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
    65 #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
    66 #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
    67 #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
     58#define cp0_mask_all_int() \
     59        cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
    6860
    69 #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
    70   { \
    71       uint32_t retval; \
    72       asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \
    73       return retval; \
    74   }
     61#define cp0_unmask_all_int() \
     62        cp0_status_write(cp0_status_read() | cp0_status_im_mask)
    7563
    76 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
    77  { \
    78     asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \
    79  }
     64#define cp0_mask_int(it) \
     65        cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
     66
     67#define cp0_unmask_int(it) \
     68        cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
     69
     70#define GEN_READ_CP0(nm, reg) \
     71        static inline uint32_t cp0_ ##nm##_read(void) \
     72        { \
     73                uint32_t retval; \
     74                \
     75                asm volatile ( \
     76                        "mfc0 %0, $" #reg \
     77                        : "=r"(retval) \
     78                ); \
     79                \
     80                return retval; \
     81        }
     82
     83#define GEN_WRITE_CP0(nm, reg) \
     84        static inline void cp0_ ##nm##_write(uint32_t val) \
     85        { \
     86                asm volatile ( \
     87                        "mtc0 %0, $" #reg \
     88                        :: "r"(val) \
     89                ); \
     90        }
    8091
    8192GEN_READ_CP0(index, 0);
Note: See TracChangeset for help on using the changeset viewer.