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Changeset db6e419 in mainline for kernel/arch/arm32/include/regutils.h


Ignore:
Timestamp:
2011-08-16T18:53:00Z (10 years ago)
Author:
Petr Koupy <petr.koupy@…>
Branches:
lfn, master
Children:
49160c4
Parents:
e0e922d (diff), 45058baa (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/regutils.h

    re0e922d rdb6e419  
    3030 * @{
    3131 */
    32 /** 
     32/**
    3333 * @file
    3434 * @brief Utilities for convenient manipulation with ARM registers.
     
    3838#define KERN_arm32_REGUTILS_H_
    3939
    40 #define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
    41 #define STATUS_REG_MODE_MASK        0x1f
     40#define STATUS_REG_IRQ_DISABLED_BIT  (1 << 7)
     41#define STATUS_REG_MODE_MASK         0x1f
    4242
    43 #define CP15_R1_HIGH_VECTORS_BIT    (1 << 13)
    44 
     43#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
    4544
    4645/* ARM Processor Operation Modes */
    47 #define USER_MODE         0x10
    48 #define FIQ_MODE          0x11
    49 #define IRQ_MODE          0x12
    50 #define SUPERVISOR_MODE   0x13
    51 #define ABORT_MODE        0x17
    52 #define UNDEFINED_MODE    0x1b
    53 #define SYSTEM_MODE       0x1f
     46#define USER_MODE        0x10
     47#define FIQ_MODE         0x11
     48#define IRQ_MODE         0x12
     49#define SUPERVISOR_MODE  0x13
     50#define ABORT_MODE       0x17
     51#define UNDEFINED_MODE   0x1b
     52#define SYSTEM_MODE      0x1f
    5453
    5554/* [CS]PRS manipulation macros */
    56 #define GEN_STATUS_READ(nm,reg) \
    57 static inline uint32_t nm## _status_reg_read(void) \
    58 { \
    59         uint32_t retval; \
    60         asm volatile( \
    61                 "mrs %[retval], " #reg \
    62                 : [retval] "=r" (retval) \
    63         ); \
    64         return retval; \
    65 }
     55#define GEN_STATUS_READ(nm, reg) \
     56        static inline uint32_t nm## _status_reg_read(void) \
     57        { \
     58                uint32_t retval; \
     59                \
     60                asm volatile ( \
     61                        "mrs %[retval], " #reg \
     62                        : [retval] "=r" (retval) \
     63                ); \
     64                \
     65                return retval; \
     66        }
    6667
    67 #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
    68 static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
    69 { \
    70         asm volatile( \
    71                 "msr " #reg "_" #field ", %[value]" \
    72                 :: [value] "r" (value) \
    73         ); \
    74 }
     68#define GEN_STATUS_WRITE(nm, reg, fieldname, field) \
     69        static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
     70        { \
     71                asm volatile ( \
     72                        "msr " #reg "_" #field ", %[value]" \
     73                        :: [value] "r" (value) \
     74                ); \
     75        }
    7576
     77/** Return the value of CPSR (Current Program Status Register). */
     78GEN_STATUS_READ(current, cpsr);
    7679
    77 /** Returns the value of CPSR (Current Program Status Register). */
    78 GEN_STATUS_READ(current, cpsr)
    79 
    80 
    81 /** Sets control bits of CPSR. */
     80/** Set control bits of CPSR. */
    8281GEN_STATUS_WRITE(current, cpsr, control, c);
    8382
    84 
    85 /** Returns the value of SPSR (Saved Program Status Register). */
    86 GEN_STATUS_READ(saved, spsr)
    87 
     83/** Return the value of SPSR (Saved Program Status Register). */
     84GEN_STATUS_READ(saved, spsr);
    8885
    8986#endif
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