Changeset da1bafb in mainline for kernel/arch/ppc32/src/mm/tlb.c
- Timestamp:
- 2010-05-24T18:57:31Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0095368
- Parents:
- 666f492
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ppc32/src/mm/tlb.c
r666f492 rda1bafb 45 45 46 46 static unsigned int seed = 10; 47 static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;48 47 static unsigned int seed_real 48 __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; 49 49 50 50 /** Try to find PTE for faulting address … … 54 54 * if lock is true. 55 55 * 56 * @param as 57 * @param lock 58 * @param badvaddr 59 * @param access 60 * @param istate 61 * @param pfrc 62 * 63 * @return PTE on success, NULL otherwise.64 * 65 * /66 static pte_t * 67 find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access,68 i state_t *istate, int *pfrc)56 * @param as Address space. 57 * @param lock Lock/unlock the address space. 58 * @param badvaddr Faulting virtual address. 59 * @param access Access mode that caused the fault. 60 * @param istate Pointer to interrupted state. 61 * @param pfrc Pointer to variable where as_page_fault() return code 62 * will be stored. 63 * 64 * @return PTE on success, NULL otherwise. 65 * 66 */ 67 static pte_t *find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, 68 int access, istate_t *istate, int *pfrc) 69 69 { 70 70 /* 71 71 * Check if the mapping exists in page tables. 72 */ 72 */ 73 73 pte_t *pte = page_mapping_find(as, badvaddr); 74 74 if ((pte) && (pte->present)) { … … 79 79 return pte; 80 80 } else { 81 int rc;82 83 81 /* 84 82 * Mapping not found in page tables. … … 86 84 */ 87 85 page_table_unlock(as, lock); 88 switch (rc = as_page_fault(badvaddr, access, istate)) { 86 87 int rc = as_page_fault(badvaddr, access, istate); 88 switch (rc) { 89 89 case AS_PF_OK: 90 90 /* … … 107 107 default: 108 108 panic("Unexpected rc (%d).", rc); 109 } 110 } 111 } 112 109 } 110 } 111 } 113 112 114 113 static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) … … 123 122 } 124 123 125 126 124 static void pht_insert(const uintptr_t vaddr, const pte_t *pte) 127 125 { … … 129 127 uint32_t api = (vaddr >> 22) & 0x3f; 130 128 131 uint32_t vsid; 132 asm volatile ( 133 "mfsrin %0, %1\n" 134 : "=r" (vsid) 135 : "r" (vaddr) 136 ); 137 138 uint32_t sdr1; 139 asm volatile ( 140 "mfsdr1 %0\n" 141 : "=r" (sdr1) 142 ); 129 uint32_t vsid = sr_get(vaddr); 130 uint32_t sdr1 = sdr1_get(); 131 132 // FIXME: compute size of PHT exactly 143 133 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); 144 134 … … 215 205 } 216 206 217 218 207 /** Process Instruction/Data Storage Exception 219 208 * … … 224 213 void pht_refill(int n, istate_t *istate) 225 214 { 226 uintptr_t badvaddr;227 pte_t *pte;228 int pfrc;229 215 as_t *as; 230 216 bool lock; … … 238 224 } 239 225 226 uintptr_t badvaddr; 227 240 228 if (n == VECTOR_DATA_STORAGE) 241 229 badvaddr = istate->dar; 242 230 else 243 231 badvaddr = istate->pc; 244 232 245 233 page_table_lock(as, lock); 246 234 247 pte = find_mapping_and_check(as, lock, badvaddr, 235 int pfrc; 236 pte_t *pte = find_mapping_and_check(as, lock, badvaddr, 248 237 PF_ACCESS_READ /* FIXME */, istate, &pfrc); 238 249 239 if (!pte) { 250 240 switch (pfrc) { … … 264 254 } 265 255 266 pte->accessed = 1; /* Record access to PTE */ 256 /* Record access to PTE */ 257 pte->accessed = 1; 267 258 pht_insert(badvaddr, pte); 268 259 … … 274 265 pht_refill_fail(badvaddr, istate); 275 266 } 276 277 267 278 268 /** Process Instruction/Data Storage Exception in Real Mode … … 291 281 badvaddr = istate->pc; 292 282 293 uint32_t physmem; 294 asm volatile ( 295 "mfsprg3 %0\n" 296 : "=r" (physmem) 297 ); 283 uint32_t physmem = physmem_top(); 298 284 299 285 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) … … 303 289 uint32_t api = (badvaddr >> 22) & 0x3f; 304 290 305 uint32_t vsid; 306 asm volatile ( 307 "mfsrin %0, %1\n" 308 : "=r" (vsid) 309 : "r" (badvaddr) 310 ); 311 312 uint32_t sdr1; 313 asm volatile ( 314 "mfsdr1 %0\n" 315 : "=r" (sdr1) 316 ); 291 uint32_t vsid = sr_get(badvaddr); 292 uint32_t sdr1 = sdr1_get(); 293 294 // FIXME: compute size of PHT exactly 317 295 phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); 318 296 … … 396 374 } 397 375 398 399 376 /** Process ITLB/DTLB Miss Exception in Real Mode 400 377 * … … 404 381 { 405 382 uint32_t badvaddr = tlbmiss & 0xfffffffc; 406 407 uint32_t physmem; 408 asm volatile ( 409 "mfsprg3 %0\n" 410 : "=r" (physmem) 411 ); 383 uint32_t physmem = physmem_top(); 412 384 413 385 if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) … … 420 392 uint32_t index = 0; 421 393 asm volatile ( 422 "mtspr 981, % 0\n"423 "mtspr 982, % 1\n"424 "tlbld % 2\n"425 "tlbli % 2\n"426 : "=r" (index)427 : "r" (ptehi),428 "r" (ptelo)394 "mtspr 981, %[ptehi]\n" 395 "mtspr 982, %[ptelo]\n" 396 "tlbld %[index]\n" 397 "tlbli %[index]\n" 398 : [index] "=r" (index) 399 : [ptehi] "r" (ptehi), 400 [ptelo] "r" (ptelo) 429 401 ); 430 402 } 431 403 432 433 404 void tlb_arch_init(void) 434 405 { … … 436 407 } 437 408 438 439 409 void tlb_invalidate_all(void) 440 410 { 441 411 uint32_t index; 412 442 413 asm volatile ( 443 "li % 0, 0\n"414 "li %[index], 0\n" 444 415 "sync\n" 445 416 446 417 ".rept 64\n" 447 " tlbie %0\n"448 " addi %0, %0, 0x1000\n"418 " tlbie %[index]\n" 419 " addi %[index], %[index], 0x1000\n" 449 420 ".endr\n" 450 421 … … 452 423 "tlbsync\n" 453 424 "sync\n" 454 : "=r" (index)425 : [index] "=r" (index) 455 426 ); 456 427 } 457 428 458 459 429 void tlb_invalidate_asid(asid_t asid) 460 430 { 461 uint32_t sdr1; 462 asm volatile ( 463 "mfsdr1 %0\n" 464 : "=r" (sdr1) 465 ); 431 uint32_t sdr1 = sdr1_get(); 432 433 // FIXME: compute size of PHT exactly 466 434 phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); 467 435 468 uint32_t i;436 size_t i; 469 437 for (i = 0; i < 8192; i++) { 470 438 if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && … … 472 440 phte[i].v = 0; 473 441 } 442 474 443 tlb_invalidate_all(); 475 444 } 476 477 445 478 446 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) … … 482 450 } 483 451 484 485 452 #define PRINT_BAT(name, ureg, lreg) \ 486 453 asm volatile ( \ 487 "mfspr %0," #ureg "\n" \ 488 "mfspr %1," #lreg "\n" \ 489 : "=r" (upper), "=r" (lower) \ 454 "mfspr %[upper], " #ureg "\n" \ 455 "mfspr %[lower], " #lreg "\n" \ 456 : [upper] "=r" (upper), \ 457 [lower] "=r" (lower) \ 490 458 ); \ 459 \ 491 460 mask = (upper & 0x1ffc) >> 2; \ 492 461 if (upper & 3) { \ 493 462 uint32_t tmp = mask; \ 494 463 length = 128; \ 464 \ 495 465 while (tmp) { \ 496 466 if ((tmp & 1) == 0) { \ … … 503 473 } else \ 504 474 length = 0; \ 475 \ 505 476 printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ 506 477 sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ … … 515 486 516 487 for (sr = 0; sr < 16; sr++) { 517 uint32_t vsid; 518 asm volatile ( 519 "mfsrin %0, %1\n" 520 : "=r" (vsid) 521 : "r" (sr << 28) 522 ); 488 uint32_t vsid = sr_get(sr << 28); 489 523 490 printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, 524 491 sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4,
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