Changeset d92bf462 in mainline for kernel/arch/ppc32/include/barrier.h

Timestamp:

2010-05-22T22:31:17Z (14 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ba7371f9

Parents:

d354d57

Message:

coding style changes, no change in functionality

File:

• kernel/arch/ppc32/include/barrier.h (modified) (3 diffs)

kernel/arch/ppc32/include/barrier.h

@@ -27 +27 @@
  */
 
-/** @addtogroup ppc32   
+/** @addtogroup ppc32
  * @{
  */
@@ -36 +36 @@
 #define KERN_ppc32_BARRIER_H_
 
-#define CS_ENTER_BARRIER()      asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()      asm volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
+#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
-#define memory_barrier() asm volatile ("sync" ::: "memory")
-#define read_barrier() asm volatile ("sync" ::: "memory")
-#define write_barrier() asm volatile ("eieio" ::: "memory")
+#define memory_barrier()  asm volatile ("sync" ::: "memory")
+#define read_barrier()    asm volatile ("sync" ::: "memory")
+#define write_barrier()   asm volatile ("eieio" ::: "memory")
+
+#define instruction_barrier() \
+        asm volatile ( \
+                "sync\n" \
+                "isync\n" \
+        )
+
+#define COHERENCE_INVAL_MIN  4
 
 /*
@@ -53 +61 @@
 {
         asm volatile (
-                "dcbst 0, %0\n"
+                "dcbst 0, %[addr]\n"
                 "sync\n"
-                "icbi 0, %0\n"
+                "icbi 0, %[addr]\n"
                 "sync\n"
                 "isync\n"
-                :: "r" (addr)
+                :: [addr] "r" (addr)
         );
 }
 
-#define COHERENCE_INVAL_MIN     4
-
-static inline void smc_coherence_block(void *addr, unsigned long len)
+static inline void smc_coherence_block(void *addr, unsigned int len)
 {
-        unsigned long i;
-
-        for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
-                asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
-        }
-
-        asm volatile ("sync");
-
-        for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
-                asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
-        }
-
-        asm volatile (
-                "sync\n"
-                "isync\n"
-        );
+        unsigned int i;
+        
+        for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
+                asm volatile (
+                        "dcbst 0, %[addr]\n"
+                        :: [addr] "r" (addr + i)
+                );
+        
+        memory_barrier();
+        
+        for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
+                asm volatile (
+                        "icbi 0, %[addr]\n"
+                        :: [addr] "r" (addr + i)
+                );
+        
+        instruction_barrier();
 }