Changeset d6f9fff in mainline for kernel/arch/ia32/include/arch/asm.h

Timestamp:

2016-04-27T12:39:14Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1a5eca4

Parents:

8a36bc1e

Message:

ia32: Make TLS settable from uspace

The TLS document[1] mandates that %gs[0] is the thread pointer on ia32.
That is good as it allows userspace-only TLS management for fibrils:
fibril_save/restore() simply manipulate the thread pointer in %gs:0 and
don't need to ask the kernel to modify %gs's base. The kernel treats
%gs:0 as another preserved register and preserves it across context
switches. GCC gets in the way a little bit because it by default assumes
that TLS is accessible from negative %gs offsets (which would
necessitate a kernel-assisted solution). Fortunately, there is a GCC
option to suppress this assumption.

• Introduce the concept of virtual registers, with VREG_TP (thread pointer) being the first of them
• Preserve VREG_TP in context_save/restore()
• Stop using sys_tls_set() in favour of using %gs:0 as the thread pointer
• Make GCC generate code that always goes through %gs:0 to access TLS

[1] Drepper, U.: ELF Handling For Thread-Local Storage

File:

• kernel/arch/ia32/include/arch/asm.h (modified) (1 diff)

kernel/arch/ia32/include/arch/asm.h

@@ -439 +439 @@
         asm volatile (
                 "ltr %[sel]"
+                :: [sel] "r" (sel)
+        );
+}
+
+/** Load GS from descriptor table.
+ *
+ * @param sel Selector specifying descriptor of the GS segment.
+ *
+ */
+NO_TRACE static inline void gs_load(uint16_t sel)
+{
+        asm volatile (
+                "mov %[sel], %%gs"
                 :: [sel] "r" (sel)
         );