Changeset d5610b9 in mainline


Ignore:
Timestamp:
2015-10-03T08:37:37Z (9 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
afe5e09
Parents:
8ca6f08
Message:

Cleanup some of the cache maintenance mess on ARM

  • Do not define ARMv7 cache maintenance registers for ARMv6-.
  • Define missing ARMv6- registers using analoguos naming convention.
  • In smc_coherence() and pt_coherence_m(), do not blindly use ARMv7 DCCVMAU but decide the proper type of cache maintenance operation in dcache_clean_mva_pou().
  • Also, do not use ARMv7 ICIALLU directly, but call icache_invalidate() instead, which does the right thing.
Location:
kernel/arch/arm32
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/arch/barrier.h

    r8ca6f08 rd5610b9  
    3838
    3939#ifdef KERNEL
     40#include <arch/cache.h>
    4041#include <arch/cp15.h>
    4142#else
    … …  
    7172 * CP15 implementation is mandatory only for armv6+.
    7273 */
     74#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    7375#define memory_barrier()  CP15DMB_write(0)
    74 #define read_barrier()    CP15DSB_write(0)
     76#else
     77#define memory_barrier()  CP15DSB_write(0)
     78#endif
     79#define read_barrier()    CP15DSB_write(0)
    7580#define write_barrier()   read_barrier()
     81#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    7682#define inst_barrier()    CP15ISB_write(0)
     83#else
     84#define inst_barrier()
     85#endif
    7786#else
    7887/* Older manuals mention syscalls as a way to implement cache coherency and
    … …  
    103112
    104113#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
    105 /* Available on all supported arms,
    106  * invalidates entire ICache so the written value does not matter. */
    107114//TODO might be PL1 only on armv5-
    108115#define smc_coherence(a) \
    109116do { \
    110         DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
     117        dcache_clean_mva_pou((uintptr_t) a);\
    111118        write_barrier();               /* Wait for completion */\
    112         ICIALLU_write(0);              /* Flush ICache */\
     119        icache_invalidate();\
    113120        inst_barrier();                /* Wait for Inst refetch */\
    114121} while (0)

  • kernel/arch/arm32/include/arch/cache.h

    r8ca6f08 rd5610b9  
    3737#define KERN_arm32_CACHE_H_
    3838
     39#include <typedefs.h>
     40
    3941unsigned dcache_levels(void);
    4042
    … …  
    4345void cpu_dcache_flush(void);
    4446void cpu_dcache_flush_invalidate(void);
    45 void icache_invalidate(void);
     47extern void icache_invalidate(void);
     48extern void dcache_clean_mva_pou(uintptr_t);
    4649
    4750#endif

  • kernel/arch/arm32/include/arch/cp15.h

    r8ca6f08 rd5610b9  
    391391CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
    392392
    393 /* Cache maintenance, address translation and other */
    394 CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */
    395 CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
    396 CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
    397 CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0);
    398 CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0);
    399 CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0);   /* PAE */
    400 CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0);   /* PAE */
    401 CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
    402 CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
     393/*
     394 * Cache maintenance, address translation and other
     395 */
     396
     397#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    403398CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
    404399CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
    405400CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
    406 
     401#endif
     402
     403#if !defined(PROCESSOR_arm920t)
     404CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
     405#endif
     406
     407#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     408CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
     409#endif
     410
     411CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
     412
     413#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
     414CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
     415#endif
     416
     417#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     418CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
     419#endif
     420
     421#if defined(PROCESSOR_ARCH_armv7_a)
     422CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
     423CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
     424CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0); /* Security Extensions */
     425CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); /* Security Extensions */
     426CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
     427CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
    407428CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
    408 CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
    409 
    410 CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
    411 CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1);
    412 CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
    413 CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
    414 CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
    415 CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
    416 CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
    417 CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
    418 
    419 
     429CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */
     430CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
     431CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); /* Security Extensions */
     432CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); /* Security Extensions */
     433CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); /* Security Extensions */
     434CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); /* Security Extensions */
     435CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); /* Security Extensions */
     436CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); /* Security Extensions */
     437CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); /* Security Extensions */
     438CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); /* Security Extensions */
     439CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); /* Virtualization Extensions */
     440CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); /* Virtualization Extensions */
    420441CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
    421 CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
    422 CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
    423 CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
    424442CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
    425 
    426 CONTROL_REG_GEN_WRITE(PFI, c7, 0, c13, 1); /* armv6 only */
    427 
    428443CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
    429 CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
    430 
    431 CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0);
    432 CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1);
     444#else
     445
     446#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     447CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4);
     448#endif
     449
     450CONTROL_REG_GEN_WRITE(ICIALL, c7, 0, c5, 0);
     451CONTROL_REG_GEN_WRITE(ICIMVA, c7, 0, c5, 1);
     452
     453#if !defined(PROCESSOR_ARCH_armv4)
     454CONTROL_REG_GEN_WRITE(ICISW, c7, 0, c5, 2);
     455#endif
     456
     457CONTROL_REG_GEN_WRITE(DCIALL, c7, 0, c6, 0);
     458CONTROL_REG_GEN_WRITE(DCIMVA, c7, 0, c6, 1);
     459CONTROL_REG_GEN_WRITE(CIALL, c7, 0, c7, 0);
     460CONTROL_REG_GEN_WRITE(CIMVA, c7, 0, c7, 1);
     461
     462#if !defined(PROCESSOR_ARCH_armv4)
     463CONTROL_REG_GEN_WRITE(CISW, c7, 0, c7, 2);
     464#endif
     465
     466#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     467CONTROL_REG_GEN_WRITE(DCCALL, c7, 0, c10, 0);
     468#endif
     469
     470CONTROL_REG_GEN_WRITE(DCCMVA, c7, 0, c10, 1);
     471
     472#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     473CONTROL_REG_GEN_WRITE(CCALL, c7, 0, c11, 0);
     474#endif
     475
     476CONTROL_REG_GEN_WRITE(CCMVA, c7, 0, c11, 1);
     477
     478#if !defined(PROCESSOR_ARCH_armv4)
     479CONTROL_REG_GEN_WRITE(CCSW, c7, 0, c11, 2);
     480#endif
     481
     482#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     483CONTROL_REG_GEN_WRITE(PFIMVA, c7, 0, c13, 1);
     484#endif
     485
     486#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     487CONTROL_REG_GEN_WRITE(DCCIALL, c7, 0, c14, 0);
     488#endif
     489
     490CONTROL_REG_GEN_WRITE(DCCIMVA, c7, 0, c14, 1);
     491
     492#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     493CONTROL_REG_GEN_WRITE(CCIALL, c7, 0, c15, 0);
     494#endif
     495
     496CONTROL_REG_GEN_WRITE(CCIMVA, c7, 0, c15, 1);
     497
     498#if defined(PROCESSOR_ARCH_armv5) || defined(PROCESSOR_ARCH_armv6)
     499CONTROL_REG_GEN_WRITE(CCISW, c7, 0, c15, 2);
     500#endif
     501
     502#endif
    433503
    434504/* TLB maintenance */

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    r8ca6f08 rd5610b9  
    123123do { \
    124124        for (unsigned i = 0; i < count; ++i) \
    125                 DCCMVAU_write((uintptr_t)(pt + i)); \
     125                dcache_clean_mva_pou((uintptr_t)(pt + i)); \
    126126        read_barrier(); \
    127127} while (0)

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    r8ca6f08 rd5610b9  
    156156do { \
    157157        for (unsigned i = 0; i < count; ++i) \
    158                 DCCMVAU_write((uintptr_t)(pt + i)); \
     158                dcache_clean_mva_pou((uintptr_t)(pt + i)); \
    159159        read_barrier(); \
    160160} while (0)
    161 
    162161
    163162/** Returns level 0 page table entry flags.

  • kernel/arch/arm32/src/cpu/cpu.c

    r8ca6f08 rd5610b9  
    322322void icache_invalidate(void)
    323323{
     324#if defined(PROCESSOR_ARCH_armv7_a)
    324325        ICIALLU_write(0);
     326#else
     327        ICIALL_write(0);
     328#endif
     329}
     330
     331#if !defined(PROCESSOR_ARCH_armv7_a)
     332static bool cache_is_unified(void)
     333{
     334        if (MIDR_read() != CTR_read()) {
     335                /* We have the CTR register */
     336                return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
     337        } else {
     338                panic("Unknown cache type");
     339        }
     340}
     341#endif
     342
     343void dcache_clean_mva_pou(uintptr_t mva)
     344{
     345#if defined(PROCESSOR_ARCH_armv7_a)
     346        DCCMVAU_write(mva);
     347#else
     348        if (cache_is_unified())
     349                CCMVA_write(mva);
     350        else
     351                DCCMVA_write(mva);
     352#endif
    325353}
    326354
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