Index: HelenOS.config
===================================================================
--- HelenOS.config	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ HelenOS.config	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -65,5 +65,4 @@
 @ "testarm" GXEmul Testarm
 @ "integratorcp" Integratorcp
-@ "beagleboardxm" BeogleBoard-xM
 ! [PLATFORM=arm32] MACHINE (choice)
 
@@ -87,17 +86,4 @@
 ! [PLATFORM=sparc64&MACHINE=generic] PROCESSOR (choice)
 
-% CPU type
-@ "armv4" ARMv4
-! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=gxemul)] PROCESSOR (choice)
-
-% CPU type
-@ "armv5" ARMv5
-! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
-
-% CPU type
-@ "armv7" ARMv7
-! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
-
-
 % RAM disk format
 @ "tmpfs" TMPFS image
@@ -422,5 +408,5 @@
 % Output device class
 @ "generic" Monitor or serial line
-! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
+! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp)] CONFIG_HID_OUT (choice)
 
 % Output device class
@@ -479,7 +465,4 @@
 ! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
 
-% Support for TI AMDM37X on-chip UART
-! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
-
 % Support for i8042 controller
 ! [CONFIG_PC_KBD=y] CONFIG_I8042 (y)
@@ -501,5 +484,5 @@
 
 % Serial line input module
-! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=beagleboardxm)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
+! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
 
 % EGA support
Index: boot/Makefile.uboot
===================================================================
--- boot/Makefile.uboot	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/Makefile.uboot	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -40,5 +40,5 @@
 
 $(POST_OUTPUT): $(BIN_OUTPUT)
-	$(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) $< $@
+	$(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr 0x30008000 -saddr 0x30008000 $< $@
 
 clean:
Index: boot/arch/arm32/Makefile.inc
===================================================================
--- boot/arch/arm32/Makefile.inc	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/Makefile.inc	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -30,14 +30,4 @@
 	BOOT_OUTPUT = image.boot
 	POST_OUTPUT = $(ROOT_PATH)/uImage.bin
-	LADDR = 0x30008000
-	SADDR = 0x30008000
-	POSTBUILD = Makefile.uboot
-endif
-
-ifeq ($(MACHINE), beagleboardxm)
-	BOOT_OUTPUT = image.boot
-	POST_OUTPUT = $(ROOT_PATH)/uImage.bin
-	LADDR = 0x80000000
-	SADDR = 0x80000000
 	POSTBUILD = Makefile.uboot
 endif
@@ -51,24 +41,10 @@
 EXTRA_CFLAGS = -march=armv4
 
-ifeq ($(MACHINE), gta02)
 RD_SRVS_ESSENTIAL += \
 	$(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24ts \
 	$(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
-endif
 
-ifeq ($(MACHINE), gxemul)
 RD_SRVS_NON_ESSENTIAL += \
 	$(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd
-endif
-
-RD_DRVS += \
-	infrastructure/rootamdm37x \
-	bus/usb/ehci \
-	bus/usb/ohci \
-	bus/usb/usbflbk \
-	bus/usb/usbhub \
-	bus/usb/usbhid \
-	bus/usb/usbmast \
-	bus/usb/usbmid
 
 SOURCES = \
Index: boot/arch/arm32/include/arch.h
===================================================================
--- boot/arch/arm32/include/arch.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/include/arch.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -42,6 +42,4 @@
 #ifdef MACHINE_gta02
 #define BOOT_BASE	0x30008000
-#elif defined MACHINE_beagleboardxm
-#define BOOT_BASE	0x80000000
 #else
 #define BOOT_BASE	0x00000000
@@ -50,16 +48,9 @@
 #define BOOT_OFFSET	(BOOT_BASE + 0xa00000)
 
-#ifdef MACHINE_beagleboardxm
-	#define PA_OFFSET 0
+#ifndef __ASM__
+	#define PA2KA(addr)  (((uintptr_t) (addr)) + 0x80000000)
 #else
-	#define PA_OFFSET 0x80000000
+	#define PA2KA(addr)  ((addr) + 0x80000000)
 #endif
-
-#ifndef __ASM__
-	#define PA2KA(addr)  (((uintptr_t) (addr)) + PA_OFFSET)
-#else
-	#define PA2KA(addr)  ((addr) + PA_OFFSET)
-#endif
-
 
 #endif
Index: boot/arch/arm32/include/main.h
===================================================================
--- boot/arch/arm32/include/main.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/include/main.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -40,16 +40,4 @@
 /** Address where characters to be printed are expected. */
 
-
-/** BeagleBoard-xM UART register address
- *
- * This is UART3 of AM/DM37x CPU
- */
-#define BBXM_SCONS_THR          0x49020000
-#define BBXM_SCONS_SSR          0x49020044
-
-/* Check this bit before writing (tx fifo full) */
-#define BBXM_THR_FULL           0x00000001
-
-
 /** GTA02 serial console UART register addresses.
  *
Index: boot/arch/arm32/include/mm.h
===================================================================
--- boot/arch/arm32/include/mm.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/include/mm.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -58,13 +58,9 @@
 	unsigned int bufferable : 1;
 	unsigned int cacheable : 1;
-	unsigned int xn : 1;
+	unsigned int impl_specific : 1;
 	unsigned int domain : 4;
 	unsigned int should_be_zero_1 : 1;
-	unsigned int access_permission_0 : 2;
-	unsigned int tex : 3;
-	unsigned int access_permission_1 : 2;
-	unsigned int non_global : 1;
-	unsigned int should_be_zero_2 : 1;
-	unsigned int non_secure : 1;
+	unsigned int access_permission : 2;
+	unsigned int should_be_zero_2 : 8;
 	unsigned int section_base_addr : 12;
 } __attribute__((packed)) pte_level0_section_t;
Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/src/mm.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -54,15 +54,11 @@
 {
 	pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
-	pte->bufferable = 1;
+	pte->bufferable = 0;
 	pte->cacheable = 0;
-	pte->xn = 0;
+	pte->impl_specific = 0;
 	pte->domain = 0;
 	pte->should_be_zero_1 = 0;
-	pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
-	pte->tex = 0;
-	pte->access_permission_1 = 0;
-	pte->non_global = 0;
+	pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
 	pte->should_be_zero_2 = 0;
-	pte->non_secure = 0;
 	pte->section_base_addr = frame;
 }
@@ -71,5 +67,6 @@
 static void init_boot_pt(void)
 {
-	const pfn_t split_page = PTL0_ENTRIES;
+	pfn_t split_page = 0x800;
+	
 	/* Create 1:1 virtual-physical mapping (in lower 2 GB). */
 	pfn_t page;
@@ -81,13 +78,6 @@
 	 * (upper 2 GB), physical addresses start from 0.
 	 */
-	/* BeagleBoard-xM (MD37x) memory starts at 2GB border,
-	 * thus mapping only lower 2GB is not not enough.
-	 * Map entire AS 1:1 instead and hope it works. */
 	for (page = split_page; page < PTL0_ENTRIES; page++)
-#ifndef MACHINE_beagleboardxm
 		init_ptl0_section(&boot_pt[page], page - split_page);
-#else
-		init_ptl0_section(&boot_pt[page], page);
-#endif
 	
 	asm volatile (
@@ -105,29 +95,11 @@
 		/* Behave as a client of domains */
 		"ldr r0, =0x55555555\n"
-		"mcr p15, 0, r0, c3, c0, 0\n"
+		"mcr p15, 0, r0, c3, c0, 0\n" 
 		
-#ifdef PROCESSOR_armv7
-		/* Clean L2 cache */
-		"mov r12, #0x1\n"   //set up to invalidate L2
-		"smc #0\n"  //Call SMI monitor
-		
-		/* Read Auxiliary control register */
-		"mrc p15, 0, r0, c1, c0, 1\n"
-		/* Mask to enable L2 cache */
-		"ldr r1, =0x00000002\n"
-		"orr r0, r0, r1\n"
-		/* Store Auxiliary control register */
-		"mrc p15, 0, r0, c1, c0, 1\n"
-#endif
 		/* Current settings */
 		"mrc p15, 0, r0, c1, c0, 0\n"
 		
-#ifdef PROCESSOR_armv7
-		/* Mask to enable paging, alignment and caching */
-		"ldr r1, =0x00000007\n"
-#else
 		/* Mask to enable paging */
 		"ldr r1, =0x00000001\n"
-#endif
 		"orr r0, r0, r1\n"
 		
Index: boot/arch/arm32/src/putchar.c
===================================================================
--- boot/arch/arm32/src/putchar.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/src/putchar.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -40,26 +40,4 @@
 #include <putchar.h>
 #include <str.h>
-
-#ifdef MACHINE_beagleboardxm
-
-/** Send a byte to the amdm37x serial console.
- *
- * @param byte		Byte to send.
- */
-static void scons_sendb_bbxm(uint8_t byte)
-{
-	volatile uint32_t *thr =
-	    (volatile uint32_t *)BBXM_SCONS_THR;
-	volatile uint32_t *ssr =
-	    (volatile uint32_t *)BBXM_SCONS_SSR;
-
-	/* Wait until transmitter is empty. */
-	while ((*ssr & BBXM_THR_FULL) == 1) ;
-
-	/* Transmit byte. */
-	*thr = (uint32_t) byte;
-}
-
-#endif
 
 #ifdef MACHINE_gta02
@@ -119,7 +97,4 @@
 static void scons_sendb(uint8_t byte)
 {
-#ifdef MACHINE_beagleboardxm
-	scons_sendb_bbxm(byte);
-#endif
 #ifdef MACHINE_gta02
 	scons_sendb_gta02(byte);
Index: faults/arm32/beagleboardxm/Makefile.config
===================================================================
--- defaults/arm32/beagleboardxm/Makefile.config	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,8 +1,0 @@
-# Machine type
-MACHINE = beagleboardxm
-
-# RAM disk format
-RDFMT = tmpfs
-
-#framebuffer
-CONFIG_FB = n
Index: kernel/arch/arm32/Makefile.inc
===================================================================
--- kernel/arch/arm32/Makefile.inc	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/Makefile.inc	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -74,8 +74,4 @@
 endif
 
-ifeq ($(MACHINE),beagleboardxm)
-	ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c
-endif
-
 ifeq ($(CONFIG_PL050),y)
 	ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c
Index: kernel/arch/arm32/_link.ld.in
===================================================================
--- kernel/arch/arm32/_link.ld.in	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/_link.ld.in	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -9,6 +9,4 @@
 #ifdef MACHINE_gta02
 #define KERNEL_LOAD_ADDRESS 0xb0a08000
-#elif defined MACHINE_beagleboardxm
-#define KERNEL_LOAD_ADDRESS 0x80a00000
 #else
 #define KERNEL_LOAD_ADDRESS 0x80a00000
Index: kernel/arch/arm32/include/asm.h
===================================================================
--- kernel/arch/arm32/include/asm.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/include/asm.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -43,13 +43,7 @@
 #include <trace.h>
 
-/** No such instruction on old ARM to sleep CPU.
- *
- * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
- */
+/** No such instruction on ARM to sleep CPU. */
 NO_TRACE static inline void cpu_sleep(void)
 {
-#ifdef PROCESSOR_armv7
-	asm volatile ( "wfe" :: );
-#endif
 }
 
Index: kernel/arch/arm32/include/cpu.h
===================================================================
--- kernel/arch/arm32/include/cpu.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/include/cpu.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -41,5 +41,5 @@
 
 
-/** Struct representing ARM CPU identification. */
+/** Struct representing ARM CPU identifiaction. */
 typedef struct {
 	/** Implementator (vendor) number. */
Index: rnel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h
===================================================================
--- kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,48 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup arm32beagleboardxm beagleboardxm
- *  @brief BeagleBoard-xM platform.
- *  @ingroup arm32
- * @{
- */
-/** @file
- *  @brief BeagleBoard platform driver.
- */
-
-#ifndef KERN_arm32_beagleboardxm_H_
-#define KERN_arm32_beagleboardxm_H_
-
-#include <arch/machine_func.h>
-
-extern struct arm_machine_ops bbxm_machine_ops;
-
-#endif
-
-/** @}
- */
-
Index: kernel/arch/arm32/include/machine_func.h
===================================================================
--- kernel/arch/arm32/include/machine_func.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/include/machine_func.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -108,6 +108,4 @@
 extern size_t machine_get_irq_count(void);
 
-extern const char * machine_get_platform_name(void);
-
 #endif
 
Index: kernel/arch/arm32/include/mm/frame.h
===================================================================
--- kernel/arch/arm32/include/mm/frame.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/include/mm/frame.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -48,6 +48,4 @@
 #ifdef MACHINE_gta02
 #define BOOT_PAGE_TABLE_ADDRESS  0x30010000
-#elif defined MACHINE_beagleboardxm
-#define BOOT_PAGE_TABLE_ADDRESS  0x80008000
 #else
 #define BOOT_PAGE_TABLE_ADDRESS  0x00008000
@@ -59,6 +57,4 @@
 #ifdef MACHINE_gta02
 #define PHYSMEM_START_ADDR	0x30008000
-#elif defined MACHINE_beagleboardxm
-#define PHYSMEM_START_ADDR      0x80000000
 #else
 #define PHYSMEM_START_ADDR	0x00000000
Index: kernel/arch/arm32/include/mm/page.h
===================================================================
--- kernel/arch/arm32/include/mm/page.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/include/mm/page.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -37,13 +37,12 @@
 #define KERN_arm32_PAGE_H_
 
-#ifdef MACHINE_beagleboardxm
-#ifndef __ASM__
-#	define KA2PA(x)	((uintptr_t) (x))
-#	define PA2KA(x)	((uintptr_t) (x))
-#else
-#	define KA2PA(x)	(x)
-#	define PA2KA(x)	(x)
-#endif
-#else
+#include <arch/mm/frame.h>
+#include <mm/mm.h>
+#include <arch/exception.h>
+#include <trace.h>
+
+#define PAGE_WIDTH	FRAME_WIDTH
+#define PAGE_SIZE	FRAME_SIZE
+
 #ifndef __ASM__
 #	define KA2PA(x)	(((uintptr_t) (x)) - 0x80000000)
@@ -53,14 +52,272 @@
 #	define PA2KA(x)	((x) + 0x80000000)
 #endif
+
+/* Number of entries in each level. */
+#define PTL0_ENTRIES_ARCH 	(1 << 12)	/* 4096 */
+#define PTL1_ENTRIES_ARCH 	0
+#define PTL2_ENTRIES_ARCH 	0
+/* coarse page tables used (256 * 4 = 1KB per page) */
+#define PTL3_ENTRIES_ARCH 	(1 << 8)	/* 256 */
+
+/* Page table sizes for each level. */
+#define PTL0_SIZE_ARCH 		FOUR_FRAMES
+#define PTL1_SIZE_ARCH 		0
+#define PTL2_SIZE_ARCH 		0
+#define PTL3_SIZE_ARCH 		ONE_FRAME
+
+/* Macros calculating indices into page tables for each level. */
+#define PTL0_INDEX_ARCH(vaddr) 	(((vaddr) >> 20) & 0xfff)
+#define PTL1_INDEX_ARCH(vaddr) 	0
+#define PTL2_INDEX_ARCH(vaddr) 	0
+#define PTL3_INDEX_ARCH(vaddr) 	(((vaddr) >> 12) & 0x0ff)
+
+/* Get PTE address accessors for each level. */
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
+	((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
+#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
+	(ptl1)
+#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
+	(ptl2)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
+	((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
+
+/* Set PTE address accessors for each level. */
+#define SET_PTL0_ADDRESS_ARCH(ptl0) \
+	(set_ptl0_addr((pte_t *) (ptl0)))
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
+	(((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
+#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
+#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
+	(((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
+
+/* Get PTE flags accessors for each level. */
+#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
+	get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
+#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
+	PAGE_PRESENT
+#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
+	PAGE_PRESENT
+#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
+	get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
+
+/* Set PTE flags accessors for each level. */
+#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
+	set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
+#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
+#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
+#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
+	set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
+
+/* Macros for querying the last-level PTE entries. */
+#define PTE_VALID_ARCH(pte) \
+	(*((uint32_t *) (pte)) != 0)
+#define PTE_PRESENT_ARCH(pte) \
+	(((pte_t *) (pte))->l0.descriptor_type != 0)
+#define PTE_GET_FRAME_ARCH(pte) \
+	(((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
+#define PTE_WRITABLE_ARCH(pte) \
+	(((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
+#define PTE_EXECUTABLE_ARCH(pte) \
+	1
+
+#ifndef __ASM__
+
+/** Level 0 page table entry. */
+typedef struct {
+	/* 0b01 for coarse tables, see below for details */
+	unsigned descriptor_type : 2;
+	unsigned impl_specific : 3;
+	unsigned domain : 4;
+	unsigned should_be_zero : 1;
+
+	/* Pointer to the coarse 2nd level page table (holding entries for small
+	 * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
+	 * tables that may hold even tiny pages (1KB) but they are bigger (4KB
+	 * per table in comparison with 1KB per the coarse table)
+	 */
+	unsigned coarse_table_addr : 22;
+} ATTRIBUTE_PACKED pte_level0_t;
+
+/** Level 1 page table entry (small (4KB) pages used). */
+typedef struct {
+
+	/* 0b10 for small pages */
+	unsigned descriptor_type : 2;
+	unsigned bufferable : 1;
+	unsigned cacheable : 1;
+
+	/* access permissions for each of 4 subparts of a page
+	 * (for each 1KB when small pages used */
+	unsigned access_permission_0 : 2;
+	unsigned access_permission_1 : 2;
+	unsigned access_permission_2 : 2;
+	unsigned access_permission_3 : 2;
+	unsigned frame_base_addr : 20;
+} ATTRIBUTE_PACKED pte_level1_t;
+
+typedef union {
+	pte_level0_t l0;
+	pte_level1_t l1;
+} pte_t;
+
+/* Level 1 page tables access permissions */
+
+/** User mode: no access, privileged mode: no access. */
+#define PTE_AP_USER_NO_KERNEL_NO	0
+
+/** User mode: no access, privileged mode: read/write. */
+#define PTE_AP_USER_NO_KERNEL_RW	1
+
+/** User mode: read only, privileged mode: read/write. */
+#define PTE_AP_USER_RO_KERNEL_RW	2
+
+/** User mode: read/write, privileged mode: read/write. */
+#define PTE_AP_USER_RW_KERNEL_RW	3
+
+
+/* pte_level0_t and pte_level1_t descriptor_type flags */
+
+/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
+#define PTE_DESCRIPTOR_NOT_PRESENT	0
+
+/** pte_level0_t coarse page table flag (used in descriptor_type). */
+#define PTE_DESCRIPTOR_COARSE_TABLE	1
+
+/** pte_level1_t small page table flag (used in descriptor type). */
+#define PTE_DESCRIPTOR_SMALL_PAGE	2
+
+
+/** Sets the address of level 0 page table.
+ *
+ * @param pt Pointer to the page table to set.
+ *
+ */
+NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
+{
+	asm volatile (
+		"mcr p15, 0, %[pt], c2, c0, 0\n"
+		:: [pt] "r" (pt)
+	);
+}
+
+
+/** Returns level 0 page table entry flags.
+ *
+ * @param pt Level 0 page table.
+ * @param i  Index of the entry to return.
+ *
+ */
+NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
+{
+	pte_level0_t *p = &pt[i].l0;
+	int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
+	
+	return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
+	    (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
+	    (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
+}
+
+/** Returns level 1 page table entry flags.
+ *
+ * @param pt Level 1 page table.
+ * @param i  Index of the entry to return.
+ *
+ */
+NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
+{
+	pte_level1_t *p = &pt[i].l1;
+	
+	int dt = p->descriptor_type;
+	int ap = p->access_permission_0;
+	
+	return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
+	    ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
+	    ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
+	    ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
+	    ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
+	    ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
+	    ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
+	    (1 << PAGE_EXEC_SHIFT) |
+	    (p->bufferable << PAGE_CACHEABLE);
+}
+
+/** Sets flags of level 0 page table entry.
+ *
+ * @param pt    level 0 page table
+ * @param i     index of the entry to be changed
+ * @param flags new flags
+ *
+ */
+NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
+{
+	pte_level0_t *p = &pt[i].l0;
+	
+	if (flags & PAGE_NOT_PRESENT) {
+		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
+		/*
+		 * Ensures that the entry will be recognized as valid when
+		 * PTE_VALID_ARCH applied.
+		 */
+		p->should_be_zero = 1;
+	} else {
+		p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
+		p->should_be_zero = 0;
+	}
+}
+
+
+/** Sets flags of level 1 page table entry.
+ *
+ * We use same access rights for the whole page. When page
+ * is not preset we store 1 in acess_rigts_3 so that at least
+ * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
+ *
+ * @param pt    Level 1 page table.
+ * @param i     Index of the entry to be changed.
+ * @param flags New flags.
+ *
+ */
+NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
+{
+	pte_level1_t *p = &pt[i].l1;
+	
+	if (flags & PAGE_NOT_PRESENT) {
+		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
+		p->access_permission_3 = 1;
+	} else {
+		p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+		p->access_permission_3 = p->access_permission_0;
+	}
+	
+	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
+	
+	/* default access permission */
+	p->access_permission_0 = p->access_permission_1 = 
+	    p->access_permission_2 = p->access_permission_3 =
+	    PTE_AP_USER_NO_KERNEL_RW;
+	
+	if (flags & PAGE_USER)  {
+		if (flags & PAGE_READ) {
+			p->access_permission_0 = p->access_permission_1 = 
+			    p->access_permission_2 = p->access_permission_3 = 
+			    PTE_AP_USER_RO_KERNEL_RW;
+		}
+		if (flags & PAGE_WRITE) {
+			p->access_permission_0 = p->access_permission_1 = 
+			    p->access_permission_2 = p->access_permission_3 = 
+			    PTE_AP_USER_RW_KERNEL_RW; 
+		}
+	}
+}
+
+
+extern void page_arch_init(void);
+
+
+#endif /* __ASM__ */
+
 #endif
 
-#if defined(PROCESSOR_armv7)
-#include "page_armv7.h"
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
-#include "page_armv4.h"
-#endif
-
-#endif
-
 /** @}
  */
Index: rnel/arch/arm32/include/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/mm/page_armv4.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,316 +1,0 @@
-/*
- * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup arm32mm
- * @{
- */
-/** @file
- *  @brief Paging related declarations.
- */
-
-#ifndef KERN_arm32_PAGE_armv4_H_
-#define KERN_arm32_PAGE_armv4_H_
-
-#include <arch/mm/frame.h>
-#include <mm/mm.h>
-#include <arch/exception.h>
-#include <trace.h>
-
-#define PAGE_WIDTH	FRAME_WIDTH
-#define PAGE_SIZE	FRAME_SIZE
-
-/* Number of entries in each level. */
-#define PTL0_ENTRIES_ARCH 	(1 << 12)	/* 4096 */
-#define PTL1_ENTRIES_ARCH 	0
-#define PTL2_ENTRIES_ARCH 	0
-/* coarse page tables used (256 * 4 = 1KB per page) */
-#define PTL3_ENTRIES_ARCH 	(1 << 8)	/* 256 */
-
-/* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH 		FOUR_FRAMES
-#define PTL1_SIZE_ARCH 		0
-#define PTL2_SIZE_ARCH 		0
-#define PTL3_SIZE_ARCH 		ONE_FRAME
-
-/* Macros calculating indices into page tables for each level. */
-#define PTL0_INDEX_ARCH(vaddr) 	(((vaddr) >> 20) & 0xfff)
-#define PTL1_INDEX_ARCH(vaddr) 	0
-#define PTL2_INDEX_ARCH(vaddr) 	0
-#define PTL3_INDEX_ARCH(vaddr) 	(((vaddr) >> 12) & 0x0ff)
-
-/* Get PTE address accessors for each level. */
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
-	((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
-#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
-	(ptl1)
-#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
-	(ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
-	((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
-
-/* Set PTE address accessors for each level. */
-#define SET_PTL0_ADDRESS_ARCH(ptl0) \
-	(set_ptl0_addr((pte_t *) (ptl0)))
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
-	(((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
-#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
-#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
-	(((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
-
-/* Get PTE flags accessors for each level. */
-#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
-	get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
-#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
-	PAGE_PRESENT
-#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
-	PAGE_PRESENT
-#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
-	get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
-
-/* Set PTE flags accessors for each level. */
-#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
-	set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
-#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
-#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
-#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
-	set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
-
-/* Macros for querying the last-level PTE entries. */
-#define PTE_VALID_ARCH(pte) \
-	(*((uint32_t *) (pte)) != 0)
-#define PTE_PRESENT_ARCH(pte) \
-	(((pte_t *) (pte))->l0.descriptor_type != 0)
-#define PTE_GET_FRAME_ARCH(pte) \
-	(((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
-#define PTE_WRITABLE_ARCH(pte) \
-	(((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
-#define PTE_EXECUTABLE_ARCH(pte) \
-	1
-
-#ifndef __ASM__
-
-/** Level 0 page table entry. */
-typedef struct {
-	/* 0b01 for coarse tables, see below for details */
-	unsigned descriptor_type : 2;
-	unsigned impl_specific : 3;
-	unsigned domain : 4;
-	unsigned should_be_zero : 1;
-
-	/* Pointer to the coarse 2nd level page table (holding entries for small
-	 * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
-	 * tables that may hold even tiny pages (1KB) but they are bigger (4KB
-	 * per table in comparison with 1KB per the coarse table)
-	 */
-	unsigned coarse_table_addr : 22;
-} ATTRIBUTE_PACKED pte_level0_t;
-
-/** Level 1 page table entry (small (4KB) pages used). */
-typedef struct {
-
-	/* 0b10 for small pages */
-	unsigned descriptor_type : 2;
-	unsigned bufferable : 1;
-	unsigned cacheable : 1;
-
-	/* access permissions for each of 4 subparts of a page
-	 * (for each 1KB when small pages used */
-	unsigned access_permission_0 : 2;
-	unsigned access_permission_1 : 2;
-	unsigned access_permission_2 : 2;
-	unsigned access_permission_3 : 2;
-	unsigned frame_base_addr : 20;
-} ATTRIBUTE_PACKED pte_level1_t;
-
-typedef union {
-	pte_level0_t l0;
-	pte_level1_t l1;
-} pte_t;
-
-/* Level 1 page tables access permissions */
-
-/** User mode: no access, privileged mode: no access. */
-#define PTE_AP_USER_NO_KERNEL_NO	0
-
-/** User mode: no access, privileged mode: read/write. */
-#define PTE_AP_USER_NO_KERNEL_RW	1
-
-/** User mode: read only, privileged mode: read/write. */
-#define PTE_AP_USER_RO_KERNEL_RW	2
-
-/** User mode: read/write, privileged mode: read/write. */
-#define PTE_AP_USER_RW_KERNEL_RW	3
-
-
-/* pte_level0_t and pte_level1_t descriptor_type flags */
-
-/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
-#define PTE_DESCRIPTOR_NOT_PRESENT	0
-
-/** pte_level0_t coarse page table flag (used in descriptor_type). */
-#define PTE_DESCRIPTOR_COARSE_TABLE	1
-
-/** pte_level1_t small page table flag (used in descriptor type). */
-#define PTE_DESCRIPTOR_SMALL_PAGE	2
-
-
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-	asm volatile (
-		"mcr p15, 0, %[pt], c2, c0, 0\n"
-		:: [pt] "r" (pt)
-	);
-}
-
-
-/** Returns level 0 page table entry flags.
- *
- * @param pt Level 0 page table.
- * @param i  Index of the entry to return.
- *
- */
-NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
-{
-	pte_level0_t *p = &pt[i].l0;
-	int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
-	
-	return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
-	    (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
-	    (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
-}
-
-/** Returns level 1 page table entry flags.
- *
- * @param pt Level 1 page table.
- * @param i  Index of the entry to return.
- *
- */
-NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
-{
-	pte_level1_t *p = &pt[i].l1;
-	
-	int dt = p->descriptor_type;
-	int ap = p->access_permission_0;
-	
-	return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
-	    ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
-	    ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
-	    ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
-	    ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
-	    ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
-	    ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
-	    (1 << PAGE_EXEC_SHIFT) |
-	    (p->bufferable << PAGE_CACHEABLE);
-}
-
-/** Sets flags of level 0 page table entry.
- *
- * @param pt    level 0 page table
- * @param i     index of the entry to be changed
- * @param flags new flags
- *
- */
-NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
-{
-	pte_level0_t *p = &pt[i].l0;
-	
-	if (flags & PAGE_NOT_PRESENT) {
-		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
-		/*
-		 * Ensures that the entry will be recognized as valid when
-		 * PTE_VALID_ARCH applied.
-		 */
-		p->should_be_zero = 1;
-	} else {
-		p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-		p->should_be_zero = 0;
-	}
-}
-
-
-/** Sets flags of level 1 page table entry.
- *
- * We use same access rights for the whole page. When page
- * is not preset we store 1 in acess_rigts_3 so that at least
- * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
- *
- * @param pt    Level 1 page table.
- * @param i     Index of the entry to be changed.
- * @param flags New flags.
- *
- */
-NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
-{
-	pte_level1_t *p = &pt[i].l1;
-	
-	if (flags & PAGE_NOT_PRESENT) {
-		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
-		p->access_permission_3 = 1;
-	} else {
-		p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-		p->access_permission_3 = p->access_permission_0;
-	}
-	
-	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
-	
-	/* default access permission */
-	p->access_permission_0 = p->access_permission_1 = 
-	    p->access_permission_2 = p->access_permission_3 =
-	    PTE_AP_USER_NO_KERNEL_RW;
-	
-	if (flags & PAGE_USER)  {
-		if (flags & PAGE_READ) {
-			p->access_permission_0 = p->access_permission_1 = 
-			    p->access_permission_2 = p->access_permission_3 = 
-			    PTE_AP_USER_RO_KERNEL_RW;
-		}
-		if (flags & PAGE_WRITE) {
-			p->access_permission_0 = p->access_permission_1 = 
-			    p->access_permission_2 = p->access_permission_3 = 
-			    PTE_AP_USER_RW_KERNEL_RW; 
-		}
-	}
-}
-
-
-extern void page_arch_init(void);
-
-
-#endif /* __ASM__ */
-
-#endif
-
-/** @}
- */
Index: rnel/arch/arm32/include/mm/page_armv7.h
===================================================================
--- kernel/arch/arm32/include/mm/page_armv7.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,329 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup arm32mm
- * @{
- */
-/** @file
- *  @brief Paging related declarations.
- */
-
-#ifndef KERN_arm32_PAGE_armv7_H_
-#define KERN_arm32_PAGE_armv7_H_
-
-#include <arch/mm/frame.h>
-#include <mm/mm.h>
-#include <arch/exception.h>
-#include <trace.h>
-
-#define PAGE_WIDTH	FRAME_WIDTH
-#define PAGE_SIZE	FRAME_SIZE
-
-/* Number of entries in each level. */
-#define PTL0_ENTRIES_ARCH 	(1 << 12)	/* 4096 */
-#define PTL1_ENTRIES_ARCH 	0
-#define PTL2_ENTRIES_ARCH 	0
-/* coarse page tables used (256 * 4 = 1KB per page) */
-#define PTL3_ENTRIES_ARCH 	(1 << 8)	/* 256 */
-
-/* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH 		FOUR_FRAMES
-#define PTL1_SIZE_ARCH 		0
-#define PTL2_SIZE_ARCH 		0
-#define PTL3_SIZE_ARCH 		ONE_FRAME
-
-/* Macros calculating indices into page tables for each level. */
-#define PTL0_INDEX_ARCH(vaddr) 	(((vaddr) >> 20) & 0xfff)
-#define PTL1_INDEX_ARCH(vaddr) 	0
-#define PTL2_INDEX_ARCH(vaddr) 	0
-#define PTL3_INDEX_ARCH(vaddr) 	(((vaddr) >> 12) & 0x0ff)
-
-/* Get PTE address accessors for each level. */
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
-	((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
-#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
-	(ptl1)
-#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
-	(ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
-	((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
-
-/* Set PTE address accessors for each level. */
-#define SET_PTL0_ADDRESS_ARCH(ptl0) \
-	(set_ptl0_addr((pte_t *) (ptl0)))
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
-	(((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
-#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
-#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
-	(((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
-
-/* Get PTE flags accessors for each level. */
-#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
-	get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
-#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
-	PAGE_PRESENT
-#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
-	PAGE_PRESENT
-#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
-	get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
-
-/* Set PTE flags accessors for each level. */
-#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
-	set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
-#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
-#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
-#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
-	set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
-
-/* Macros for querying the last-level PTE entries. */
-#define PTE_VALID_ARCH(pte) \
-	(*((uint32_t *) (pte)) != 0)
-#define PTE_PRESENT_ARCH(pte) \
-	(((pte_t *) (pte))->l0.descriptor_type != 0)
-#define PTE_GET_FRAME_ARCH(pte) \
-	(((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
-#define PTE_WRITABLE_ARCH(pte) \
-	(((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO)
-#define PTE_EXECUTABLE_ARCH(pte) \
-	(((pte_t *) (pte))->l1.descriptor_type != PTE_DESCRIPTOR_SMALL_PAGE_NX)
-
-#ifndef __ASM__
-
-/** Level 0 page table entry. */
-typedef struct {
-	/* 0b01 for coarse tables, see below for details */
-	unsigned descriptor_type : 2;
-	unsigned pxn : 1;
-	unsigned ns : 1;
-	unsigned should_be_zero_0 : 1;
-	unsigned domain : 4;
-	unsigned should_be_zero_1 : 1;
-
-	/* Pointer to the coarse 2nd level page table (holding entries for small
-	 * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
-	 * tables that may hold even tiny pages (1KB) but they are bigger (4KB
-	 * per table in comparison with 1KB per the coarse table)
-	 */
-	unsigned coarse_table_addr : 22;
-} ATTRIBUTE_PACKED pte_level0_t;
-
-/** Level 1 page table entry (small (4KB) pages used). */
-typedef struct {
-
-	/* 0b10 for small pages, 0b11 for NX small pages */
-	unsigned descriptor_type : 2;
-	unsigned bufferable : 1;
-	unsigned cacheable : 1;
-	unsigned access_permission_0 : 2;
-	unsigned tex : 3;
-	unsigned access_permission_1 : 1;
-	unsigned shareable : 1;
-	unsigned non_global : 1;
-	unsigned frame_base_addr : 20;
-} ATTRIBUTE_PACKED pte_level1_t;
-
-typedef union {
-	pte_level0_t l0;
-	pte_level1_t l1;
-} pte_t;
-
-/* Level 1 page tables access permissions */
-
-/** User mode: no access, privileged mode: no access. */
-#define PTE_AP0_USER_NO_KERNEL_NO   0
-
-/** User mode: no access, privileged mode: read/write. */
-#define PTE_AP0_USER_NO_KERNEL_FULL   1
-
-/** User mode: read only, privileged mode: read/write. */
-#define PTE_AP0_USER_LIMITED_KERNEL_FULL   2
-
-/** User mode: read/write, privileged mode: read/write. */
-#define PTE_AP0_USER_FULL_KERNEL_FULL    3
-
-/** Allow writes */
-#define PTE_AP1_RO   1
-
-
-/* pte_level0_t and pte_level1_t descriptor_type flags */
-
-/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
-#define PTE_DESCRIPTOR_NOT_PRESENT	0
-
-/** pte_level0_t coarse page table flag (used in descriptor_type). */
-#define PTE_DESCRIPTOR_COARSE_TABLE	1
-
-/** pte_level1_t small page table flag (used in descriptor type). */
-#define PTE_DESCRIPTOR_SMALL_PAGE	2
-
-/** pte_level1_t small page table flag with NX (used in descriptor type). */
-#define PTE_DESCRIPTOR_SMALL_PAGE_NX	3
-
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-	asm volatile (
-		"mcr p15, 0, %[pt], c2, c0, 0\n"
-		:: [pt] "r" (pt)
-	);
-}
-
-
-/** Returns level 0 page table entry flags.
- *
- * @param pt Level 0 page table.
- * @param i  Index of the entry to return.
- *
- */
-NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
-{
-	const pte_level0_t *p = &pt[i].l0;
-	const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
-	
-	return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
-	    (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
-	    (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
-}
-
-/** Returns level 1 page table entry flags.
- *
- * @param pt Level 1 page table.
- * @param i  Index of the entry to return.
- *
- */
-NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
-{
-	const pte_level1_t *p = &pt[i].l1;
-	
-	const unsigned dt = p->descriptor_type;
-	const unsigned ap0 = p->access_permission_0;
-	const unsigned ap1 = p->access_permission_1;
-	
-	return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
-	    ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) |
-	    ((ap0 == PTE_AP0_USER_LIMITED_KERNEL_FULL) << PAGE_READ_SHIFT) |
-	    ((ap0 == PTE_AP0_USER_FULL_KERNEL_FULL) << PAGE_READ_SHIFT) |
-	    ((ap0 == PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_READ_SHIFT) |
-	    ((ap0 != PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_USER_SHIFT) |
-	    (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_FULL_KERNEL_FULL)) << PAGE_WRITE_SHIFT) |
-	    (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_NO_KERNEL_FULL)) << PAGE_WRITE_SHIFT) |
-	    (p->bufferable << PAGE_CACHEABLE);
-}
-
-/** Sets flags of level 0 page table entry.
- *
- * @param pt    level 0 page table
- * @param i     index of the entry to be changed
- * @param flags new flags
- *
- */
-NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
-{
-	pte_level0_t *p = &pt[i].l0;
-	
-	if (flags & PAGE_NOT_PRESENT) {
-		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
-		/*
-		 * Ensures that the entry will be recognized as valid when
-		 * PTE_VALID_ARCH applied.
-		 */
-		p->should_be_zero_0 = 1;
-		p->should_be_zero_1 = 1;
-	} else {
-		p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-		p->should_be_zero_0 = 0;
-		p->should_be_zero_1 = 0;
-		p->domain = 0;
-		p->ns = 0;
-	}
-}
-
-
-/** Sets flags of level 1 page table entry.
- *
- * We use same access rights for the whole page. When page
- * is not preset we store 1 in acess_rigts_3 so that at least
- * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
- *
- * @param pt    Level 1 page table.
- * @param i     Index of the entry to be changed.
- * @param flags New flags.
- *
- */
-NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
-{
-	pte_level1_t *p = &pt[i].l1;
-	
-	if (flags & PAGE_NOT_PRESENT) {
-		p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
-	} else {
-		if (flags & PAGE_EXEC)
-			p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-		else
-			p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX;
-	}
-	
-	/* tex=0 buf=1 and cache=1 => normal memory
-	 * tex=0 buf=1 and cache=0 => shareable device mmio
-	 */
-	p->cacheable = (flags & PAGE_CACHEABLE);
-	p->bufferable = 1;
-	p->tex = 0;
-	
-	/* Shareable is ignored for devices (non-cacheable),
-	 * turn it on for normal memory. */
-	p->shareable = 1;
-	
-	p->non_global = !(flags & PAGE_GLOBAL);
-	
-	/* default access permission: kernel only*/
-	p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL;
-	
-	if (flags & PAGE_USER) {
-		p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL;
-		// TODO Fix kernel to use PAGE_WRITE flag properly and
-		// apply this for kernel pages as well.
-		if (!(flags & PAGE_WRITE))
-			p->access_permission_1 = PTE_AP1_RO;
-	}
-}
-
-
-extern void page_arch_init(void);
-
-#endif /* __ASM__ */
-
-#endif
-
-/** @}
- */
Index: kernel/arch/arm32/include/regutils.h
===================================================================
--- kernel/arch/arm32/include/regutils.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/include/regutils.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -41,20 +41,5 @@
 #define STATUS_REG_MODE_MASK         0x1f
 
-#define CP15_R1_MMU_ENABLE_BIT       (1 << 0)
-#define CP15_R1_ALIGNMENT_ENABLE_BIT (1 << 1)
-#define CP15_R1_CACHE_ENABLE_BIT     (1 << 2)
-#define CP15_R1_BRANCH_PREDICT_BIT   (1 << 11)
-#define CP15_R1_INST_CACHE_BIT       (1 << 12)
 #define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
-#define CP15_R1_ROUND_ROBIN_BIT      (1 << 14)
-#define CP15_R1_HA_ENABLE_BIT        (1 << 17)
-#define CP15_R1_WXN_BIT              (1 << 19) /* Only if virt. supported */
-#define CP15_R1_UWXN_BIT             (1 << 20) /* Only if virt. supported */
-#define CP15_R1_FI_BIT               (1 << 21)
-#define CP15_R1_VE_BIT               (1 << 24)
-#define CP15_R1_EE_BIT               (1 << 25)
-#define CP15_R1_NMFI_BIT             (1 << 27)
-#define CP15_R1_TRE_BIT              (1 << 28)
-#define CP15_R1_AFE_BIT              (1 << 29)
 
 /* ARM Processor Operation Modes */
Index: kernel/arch/arm32/src/arm32.c
===================================================================
--- kernel/arch/arm32/src/arm32.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/src/arm32.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -49,5 +49,4 @@
 #include <str.h>
 #include <arch/ras.h>
-#include <sysinfo/sysinfo.h>
 
 /** Performs arm32-specific initialization before main_bsp() is called. */
@@ -117,8 +116,4 @@
 {
 	machine_input_init();
-	const char *platform = machine_get_platform_name();
-
-	sysinfo_set_item_data("platform", NULL, (void *) platform,
-	    str_size(platform));
 }
 
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -44,17 +44,14 @@
 /** Implementators (vendor) names */
 static const char *imp_data[] = {
-	"?",                                     /* IMP_DATA_START_OFFSET */
-	"ARM Limited",                           /* 0x41 */
-	"", "",                                  /* 0x42 - 0x43 */
-	"Digital Equipment Corporation",         /* 0x44 */
-	"", "", "", "", "", "", "", "",          /* 0x45 - 0x4c */
-	"Motorola, Freescale Semicondutor Inc.", /* 0x4d */
-	"", "", "",                              /* 0x4e - 0x50 */
-	"Qualcomm Inc.",                         /* 0x51 */
-	"", "", "", "",                          /* 0x52 - 0x55 */
-	"Marvell Semiconductor",                 /* 0x56 */
-	"", "", "", "", "", "", "", "", "", "",  /* 0x57 - 0x60 */
-	"", "", "", "", "", "", "", "",          /* 0x61 - 0x68 */
-	"Intel Corporation"                      /* 0x69 */
+	"?",					/* IMP_DATA_START_OFFSET */
+	"ARM Ltd",				/* 0x41 */
+	"",					/* 0x42 */
+	"",                             	/* 0x43 */
+	"Digital Equipment Corporation",	/* 0x44 */
+	"", "", "", "", "", "", "", "", "", "",	/* 0x45 - 0x4e */
+	"", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */
+	"", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */
+	"", "", "", "", "", "",			/* 0x63 - 0x68 */
+	"Intel Corporation"			/* 0x69 */
 };
 
@@ -100,23 +97,4 @@
 void cpu_arch_init(void)
 {
-#if defined(PROCESSOR_armv7)
-	uint32_t control_reg = 0;
-	asm volatile (
-		"mrc p15, 0, %[control_reg], c1, c0"
-		: [control_reg] "=r" (control_reg)
-	);
-	
-	/* Turn off tex remap */
-	control_reg &= ~CP15_R1_TRE_BIT;
-	/* Turn off accessed flag */
-	control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT);
-	/* Enable caching */
-	control_reg |= CP15_R1_CACHE_ENABLE_BIT;
-	
-	asm volatile (
-		"mcr p15, 0, %[control_reg], c1, c0"
-		:: [control_reg] "r" (control_reg)
-	);
-#endif
 }
 
@@ -134,12 +112,11 @@
 	cpu_arch_t * cpu_arch = &m->arch;
 
-	const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET;
-
-	if (imp_offset < imp_data_length) {
+	if ((cpu_arch->imp_num) > 0 &&
+	    (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) {
 		vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET];
 	}
 
-	// TODO CPUs with arch_num == 0xf use CPUID scheme for identification
-	if (cpu_arch->arch_num < arch_data_length) {
+	if ((cpu_arch->arch_num) > 0 &&
+	    (cpu_arch->arch_num < arch_data_length)) {
 		architecture = arch_data[cpu_arch->arch_num];
 	}
Index: kernel/arch/arm32/src/exception.c
===================================================================
--- kernel/arch/arm32/src/exception.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/src/exception.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -120,32 +120,18 @@
 static void high_vectors(void)
 {
-	uint32_t control_reg = 0;
+	uint32_t control_reg;
 	
-#if defined(PROCESSOR_armv7)
-	asm volatile (
-		"mrc p15, 0, %[control_reg], c1, c0"
-		: [control_reg] "=r" (control_reg)
-	);
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
 	asm volatile (
 		"mrc p15, 0, %[control_reg], c1, c1"
 		: [control_reg] "=r" (control_reg)
 	);
-#endif
 	
 	/* switch on the high vectors bit */
 	control_reg |= CP15_R1_HIGH_VECTORS_BIT;
 	
-#if defined(PROCESSOR_armv7)
-	asm volatile (
-		"mcr p15, 0, %[control_reg], c1, c0"
-		:: [control_reg] "r" (control_reg)
-	);
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
 	asm volatile (
 		"mcr p15, 0, %[control_reg], c1, c1"
 		:: [control_reg] "r" (control_reg)
 	);
-#endif
 }
 #endif
Index: rnel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,202 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup arm32beagleboardxm
- * @{
- */
-/** @file
- *  @brief BeagleBoard-xM platform driver.
- */
-
-#include <arch/exception.h>
-#include <arch/mach/beagleboardxm/beagleboardxm.h>
-#include <genarch/drivers/amdm37x_irc/amdm37x_irc.h>
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
-#include <genarch/drivers/amdm37x_gpt/amdm37x_gpt.h>
-#include <genarch/srln/srln.h>
-#include <interrupt.h>
-#include <mm/km.h>
-#include <ddi/ddi.h>
-#include <ddi/device.h>
-
-static void bbxm_init(void);
-static void bbxm_timer_irq_start(void);
-static void bbxm_cpu_halt(void);
-static void bbxm_get_memory_extents(uintptr_t *start, size_t *size);
-static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate);
-static void bbxm_frame_init(void);
-static void bbxm_output_init(void);
-static void bbxm_input_init(void);
-static size_t bbxm_get_irq_count(void);
-static const char *bbxm_get_platform_name(void);
-
-#define BBXM_MEMORY_START	0x80000000	/* physical */
-#define BBXM_MEMORY_SIZE	0x20000000	/* 512 MB */
-
-static struct beagleboard {
-	amdm37x_irc_regs_t *irc_addr;
-	amdm37x_uart_t uart;
-	amdm37x_gpt_t timer;
-} beagleboard;
-
-struct arm_machine_ops bbxm_machine_ops = {
-	.machine_init = bbxm_init,
-	.machine_timer_irq_start = bbxm_timer_irq_start,
-	.machine_cpu_halt = bbxm_cpu_halt,
-	.machine_get_memory_extents = bbxm_get_memory_extents,
-	.machine_irq_exception = bbxm_irq_exception,
-	.machine_frame_init = bbxm_frame_init,
-	.machine_output_init = bbxm_output_init,
-	.machine_input_init = bbxm_input_init,
-	.machine_get_irq_count = bbxm_get_irq_count,
-	.machine_get_platform_name = bbxm_get_platform_name
-};
-
-static irq_ownership_t bb_timer_irq_claim(irq_t *irq)
-{
-	return IRQ_ACCEPT;
-}
-
-static void bb_timer_irq_handler(irq_t *irq)
-{
-        /*
-         * We are holding a lock which prevents preemption.
-         * Release the lock, call clock() and reacquire the lock again.
-         */
-	amdm37x_gpt_irq_ack(&beagleboard.timer);
-	spinlock_unlock(&irq->lock);
-	clock();
-	spinlock_lock(&irq->lock);
-}
-
-static void bbxm_init(void)
-{
-	/* Initialize interrupt controller */
-	beagleboard.irc_addr =
-	    (void *) km_map(AMDM37x_IRC_BASE_ADDRESS, AMDM37x_IRC_SIZE,
-	    PAGE_NOT_CACHEABLE);
-	amdm37x_irc_init(beagleboard.irc_addr);
-
-
-	/* Initialize timer, pick timer1, because it is in always-power domain
-	 * and has special capabilities for regular ticks */
-	amdm37x_gpt_timer_ticks_init(&beagleboard.timer,
-	    AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ);
-}
-
-static void bbxm_timer_irq_start(void)
-{
-	/* Initialize timer IRQ */
-	static irq_t timer_irq;
-	irq_initialize(&timer_irq);
-	timer_irq.devno = device_assign_devno();
-	timer_irq.inr = AMDM37x_GPT1_IRQ;
-	timer_irq.claim = bb_timer_irq_claim;
-	timer_irq.handler = bb_timer_irq_handler;
-	irq_register(&timer_irq);
-
-	/* Enable timer interrupt */
-	amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
-
-	/* Start timer here */
-	amdm37x_gpt_timer_ticks_start(&beagleboard.timer);
-}
-
-static void bbxm_cpu_halt(void)
-{
-	while (1);
-}
-
-/** Get extents of available memory.
- *
- * @param start		Place to store memory start address (physical).
- * @param size		Place to store memory size.
- */
-static void bbxm_get_memory_extents(uintptr_t *start, size_t *size)
-{
-	*start = BBXM_MEMORY_START;
-	*size = BBXM_MEMORY_SIZE;
-}
-
-static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate)
-{
-	const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
-	amdm37x_irc_irq_ack(beagleboard.irc_addr);
-
-	irq_t *irq = irq_dispatch_and_lock(inum);
-	if (irq) {
-		/* The IRQ handler was found. */
-		irq->handler(irq);
-		spinlock_unlock(&irq->lock);
-	} else {
-		/* Spurious interrupt.*/
-		printf("cpu%d: spurious interrupt (inum=%d)\n",
-		    CPU->id, inum);
-	}
-}
-
-static void bbxm_frame_init(void)
-{
-}
-
-static void bbxm_output_init(void)
-{
-#ifdef CONFIG_FB
-#error "Frame buffer is not yet supported!"
-#endif
-	/* UART3 is wired to external RS232 connector */
-	const bool ok = amdm37x_uart_init(&beagleboard.uart,
-	    AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE);
-	if (ok) {
-		stdout_wire(&beagleboard.uart.outdev);
-	}
-}
-
-static void bbxm_input_init(void)
-{
-	srln_instance_t *srln_instance = srln_init();
-	if (srln_instance) {
-		indev_t *sink = stdin_wire();
-		indev_t *srln = srln_wire(srln_instance, sink);
-		amdm37x_uart_input_wire(&beagleboard.uart, srln);
-		amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
-	}
-}
-
-size_t bbxm_get_irq_count(void)
-{
-	return AMDM37x_IRC_IRQ_COUNT;
-}
-
-const char *bbxm_get_platform_name(void)
-{
-	return "beagleboardxm";
-}
-
-/**
- * @}
- */
Index: kernel/arch/arm32/src/machine_func.c
===================================================================
--- kernel/arch/arm32/src/machine_func.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/src/machine_func.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -42,5 +42,4 @@
 #include <arch/mach/integratorcp/integratorcp.h>
 #include <arch/mach/testarm/testarm.h>
-#include <arch/mach/beagleboardxm/beagleboardxm.h>
 
 /** Pointer to machine_ops structure being used. */
@@ -56,6 +55,4 @@
 #elif defined(MACHINE_integratorcp)
 	machine_ops = &icp_machine_ops;
-#elif defined(MACHINE_beagleboardxm)
-	machine_ops = &bbxm_machine_ops;
 #else
 #error Machine type not defined.
@@ -134,10 +131,4 @@
 }
 
-const char * machine_get_platform_name(void)
-{
-	if (machine_ops->machine_get_platform_name)
-		return machine_ops->machine_get_platform_name();
-	return NULL;
-}
 /** @}
  */
Index: kernel/arch/arm32/src/mm/page.c
===================================================================
--- kernel/arch/arm32/src/mm/page.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/arch/arm32/src/mm/page.c	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -52,16 +52,14 @@
 void page_arch_init(void)
 {
-	int flags = PAGE_CACHEABLE | PAGE_EXEC;
+	int flags = PAGE_CACHEABLE;
 	page_mapping_operations = &pt_mapping_operations;
 
 	page_table_lock(AS_KERNEL, true);
 	
+	uintptr_t cur;
+
 	/* Kernel identity mapping */
-	//FIXME: We need to consider the possibility that
-	//identity_base > identity_size and physmem_end.
-	//This might lead to overflow if identity_size is too big.
-	for (uintptr_t cur = PHYSMEM_START_ADDR;
-	    cur < min(KA2PA(config.identity_base) +
-	        config.identity_size, config.physmem_end);
+	for (cur = PHYSMEM_START_ADDR;
+	    cur < min(config.identity_size, config.physmem_end);
 	    cur += FRAME_SIZE)
 		page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
Index: kernel/genarch/Makefile.inc
===================================================================
--- kernel/genarch/Makefile.inc	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ kernel/genarch/Makefile.inc	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -101,9 +101,4 @@
 endif
 
-ifeq ($(CONFIG_AMDM37X_UART),y)
-	GENARCH_SOURCES += \
-		genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
-endif
-
 ifeq ($(CONFIG_VIA_CUDA),y)
 	GENARCH_SOURCES += \
Index: rnel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,255 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
- */
-
-#ifndef KERN_AMDM37x_GPT_H_
-#define KERN_AMDM37x_GPT_H_
-
-#include <typedefs.h>
-#include <mm/km.h>
-
-/* AMDM37x TRM p. 2740 */
-#define AMDM37x_GPT1_BASE_ADDRESS  0x48318000
-#define AMDM37x_GPT1_SIZE  4096
-#define AMDM37x_GPT1_IRQ  37
-#define AMDM37x_GPT2_BASE_ADDRESS  0x49032000
-#define AMDM37x_GPT2_SIZE  4096
-#define AMDM37x_GPT2_IRQ  38
-#define AMDM37x_GPT3_BASE_ADDRESS  0x49034000
-#define AMDM37x_GPT3_SIZE  4096
-#define AMDM37x_GPT3_IRQ  39
-#define AMDM37x_GPT4_BASE_ADDRESS  0x49036000
-#define AMDM37x_GPT4_SIZE  4096
-#define AMDM37x_GPT4_IRQ  40
-#define AMDM37x_GPT5_BASE_ADDRESS  0x49038000
-#define AMDM37x_GPT5_SIZE  4096
-#define AMDM37x_GPT5_IRQ  41
-#define AMDM37x_GPT6_BASE_ADDRESS  0x4903a000
-#define AMDM37x_GPT6_SIZE  4096
-#define AMDM37x_GPT6_IRQ  42
-#define AMDM37x_GPT7_BASE_ADDRESS  0x4903c000
-#define AMDM37x_GPT7_SIZE  4096
-#define AMDM37x_GPT7_IRQ  43
-#define AMDM37x_GPT8_BASE_ADDRESS  0x4903e000
-#define AMDM37x_GPT8_SIZE  4096
-#define AMDM37x_GPT8_IRQ  44
-#define AMDM37x_GPT9_BASE_ADDRESS  0x49040000
-#define AMDM37x_GPT9_SIZE  4096
-#define AMDM37x_GPT9_IRQ  45
-#define AMDM37x_GPT10_BASE_ADDRESS  0x48086000
-#define AMDM37x_GPT10_SIZE  4096
-#define AMDM37x_GPT10_IRQ  46
-#define AMDM37x_GPT11_BASE_ADDRESS  0x48088000
-#define AMDM37x_GPT11_SIZE  4096
-#define AMDM37x_GPT11_IRQ  47
-
-
-/** GPT register map AMDM37x TRM p. 2740 */
-typedef struct {
-	/** IP revision */
-	const ioport32_t tidr;
-#define AMDM37x_GPT_TIDR_MINOR_MASK  (0xf)
-#define AMDM37x_GPT_TIDR_MINOR_SHIFT  (0)
-#define AMDM37x_GPT_TIDR_MAJOR_MASK  (0xf)
-#define AMDM37x_GPT_TIDR_MAJOR_SHIFT  (4)
-	uint32_t padd0_[3];
-
-	/** L4 Interface parameters */
-	ioport32_t tiocp_cfg;
-#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG  (1 << 0)
-#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG  (1 << 1)
-#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG  (1 << 2)
-#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK  (0x3)
-#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT  (3)
-#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG  (1 << 5)
-#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK  (0x3)
-#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
-
-	/** Module status information, excluding irq */
-	const ioport32_t tistat;
-#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG  (1 << 0)
-
-	/** Interrupt status register */
-	ioport32_t tisr;
-#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG  (1 << 2)
-
-	/* Interrupt enable register */
-	ioport32_t tier;
-#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG  (1 << 2)
-
-	/** Wakeup enable register */
-	ioport32_t twer;
-#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG  (1 << 2)
-
-	/** Optional features control register */
-	ioport32_t tclr;
-#define AMDM37x_GPT_TCLR_ST_FLAG  (1 << 0)
-#define AMDM37x_GPT_TCLR_AR_FLAG  (1 << 1)
-#define AMDM37x_GPT_TCLR_PTV_MASK  (0x7)
-#define AMDM37x_GPT_TCLR_PTV_SHIFT  (2)
-#define AMDM37x_GPT_TCLR_PRE_FLAG  (1 << 5)
-#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
-#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
-#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
-#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
-#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
-#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
-#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG  (1 << 14)
-
-	/** Value of timer counter */
-	ioport32_t tccr;
-
-	/** Timer load register */
-	ioport32_t tldr;
-
-	/** Timer trigger register */
-	ioport32_t ttgr;
-
-	/** Write-posted pending register */
-	const ioport32_t twps;
-#define AMDM37x_GPT_TWPS_TCLR_FLAG  (1 << 0)
-#define AMDM37x_GPT_TWPS_TCRR_FLAG  (1 << 1)
-#define AMDM37x_GPT_TWPS_TLDR_FLAG  (1 << 2)
-#define AMDM37x_GPT_TWPS_TTGR_FLAG  (1 << 3)
-#define AMDM37x_GPT_TWPS_TMAR_FLAG  (1 << 4)
-#define AMDM37x_GPT_TWPS_TPIR_FLAG  (1 << 5)
-#define AMDM37x_GPT_TWPS_TNIR_FLAG  (1 << 6)
-#define AMDM37x_GPT_TWPS_TCVR_FLAG  (1 << 7)
-#define AMDM37x_GPT_TWPS_TOCR_FLAG  (1 << 8)
-#define AMDM37x_GPT_TWPS_TOWR_FLAG  (1 << 9)
-
-	/** Timer match register */
-	ioport32_t tmar;
-
-	/** Capture value 1 register */
-	const ioport32_t tcar1;
-
-	/** Software interface control register */
-	ioport32_t tsicr;
-#define AMDM37x_GPT_TSICR_SFT_FLAG  (1 << 1)
-#define AMDM37x_GPT_TSICR_POSTED_FLAG  (1 << 2)
-
-	/** Capture value 2 register */
-	const ioport32_t tcar2;
-
-	/* GPT1,2,10 only (used for 1ms time period generation)*/
-
-	/** Positive increment register */
-	ioport32_t tpir;
-
-	/** Negative increment register */
-	ioport32_t tnir;
-
-	/** Counter value register */
-	ioport32_t tcvr;
-
-	/** Mask the tick interrupt for selected number of ticks */
-	ioport32_t tocr;
-
-	/** Number of masked overflow interrupts */
-	ioport32_t towr;
-} amdm37x_gpt_regs_t;
-
-typedef struct {
-	amdm37x_gpt_regs_t *regs;
-	bool special_available;
-} amdm37x_gpt_t;
-
-static inline void amdm37x_gpt_timer_ticks_init(
-    amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
-{
-	/* Set 32768 Hz clock as source */
-	// TODO find a nicer way to setup 32kHz clock source for timer1
-	// reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
-	ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
-	*clksel &= ~1;
-	km_unmap((uintptr_t)clksel, 4);
-
-	ASSERT(timer);
-	/* Map control register */
-	timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
-
-	/* Set autoreload */
-	timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
-
-	timer->special_available = (
-	    (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
-	    (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
-	    (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
-	timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
-	timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
-	if (timer->special_available) {
-		/* Set values for according to formula (manual p. 2733) */
-		/* Use temporary variables for easier debugging */
-		const uint32_t tpir =
-		    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
-		const uint32_t tnir =
-		    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
-		timer->regs->tpir = tpir;
-		timer->regs->tnir = tnir;
-	}
-
-}
-
-static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
-{
-	ASSERT(timer);
-	ASSERT(timer->regs);
-	/* Enable overflow interrupt */
-	timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
-	/* Start timer */
-	timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
-}
-
-static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
-{
-	ASSERT(timer);
-	ASSERT(timer->regs);
-	/* Clear all pending interrupts */
-	timer->regs->tisr = timer->regs->tisr;
-}
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,207 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver.
- */
-
-#ifndef KERN_AMDM37x_IRQC_H_
-#define KERN_AMDM37x_IRQC_H_
-
-/* AMDM37x TRM p. 1079 */
-#define AMDM37x_IRC_BASE_ADDRESS 0x48200000
-#define AMDM37x_IRC_SIZE 4096
-
-#define AMDM37x_IRC_IRQ_COUNT 96
-
-#include <typedefs.h>
-
-typedef struct {
-	const ioport32_t revision; /**< Revision */
-#define AMDM37x_IRC_REV_MASK (0xff)
-
-	uint8_t padd0_[12];
-
-	ioport32_t sysconfig; /**< SYS config */
-#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
-#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
-
-	const ioport32_t sysstatus; /**< SYS status */
-#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
-
-	uint8_t padd1_[40];
-
-	const ioport32_t sir_irq;   /**< Currently active irq number */
-#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f)
-#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	const ioport32_t sir_fiq;
-#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f)
-#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	ioport32_t control;   /**< New interrupt agreement. */
-#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0)
-#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1)
-
-	ioport32_t protection;  /**< Protect other registers. */
-#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0)
-
-	ioport32_t idle;   /**< Idle and autogating */
-#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0)
-#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1)
-
-	uint8_t padd2_[12];
-
-	ioport32_t irq_priority; /**< Active IRQ priority */
-#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f)
-#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	ioport32_t fiq_priority; /**< Active FIQ priority */
-#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f)
-#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8)
-
-	ioport32_t threshold; /**< Priority threshold */
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff)
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00)
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff)
-
-	uint8_t padd3__[20];
-
-	struct {
-		const ioport32_t itr;   /**< Interrupt input status before masking */
-		ioport32_t mir;   /**< Interrupt mask */
-		ioport32_t mir_clear; /**< Clear mir mask bits */
-		ioport32_t mir_set;   /**< Set mir mask bits */
-		ioport32_t isr_set;   /**< Set software interrupt bits */
-		ioport32_t isr_clear; /**< Clear software interrupt bits */
-		const ioport32_t pending_irq; /**< IRQ status after masking */
-		const ioport32_t pending_fiq; /**< FIQ status after masking */
-	} interrupts[3];
-
-	uint8_t padd4_[32];
-
-	ioport32_t ilr[96];   /**< FIQ/IRQ steering */
-#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0)
-#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f)
-#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2)
-
-} amdm37x_irc_regs_t;
-
-static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs)
-{
-#define DUMP_REG(name) \
-	printf("%s %p(%x).\n", #name, &regs->name, regs->name);
-
-	DUMP_REG(revision);
-	DUMP_REG(sysconfig);
-	DUMP_REG(sysstatus);
-	DUMP_REG(sir_irq);
-	DUMP_REG(sir_fiq);
-	DUMP_REG(control);
-	DUMP_REG(protection);
-	DUMP_REG(idle);
-	DUMP_REG(irq_priority);
-	DUMP_REG(fiq_priority);
-	DUMP_REG(threshold);
-
-	for (int i = 0; i < 3; ++i) {
-		DUMP_REG(interrupts[i].itr);
-		DUMP_REG(interrupts[i].mir);
-		DUMP_REG(interrupts[i].isr_set);
-		DUMP_REG(interrupts[i].pending_irq);
-		DUMP_REG(interrupts[i].pending_fiq);
-	}
-	for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
-		DUMP_REG(ilr[i]);
-	}
-
-#undef DUMP_REG
-}
-
-
-static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs)
-{
-	/* AMDM37x TRM sec 12.5.1 p. 2425 */
-	/* Program system config register */
-	//TODO enable this when you know the meaning
-	//regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
-
-	/* Program idle register */
-	//TODO enable this when you know the meaning
-	//regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG;
-
-	/* Program ilr[m] assign priority, decide fiq */
-	for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
-		regs->ilr[i] = 0; /* highest prio(default) route to irq */
-	}
-
-	/* Disable all interrupts */
-	regs->interrupts[0].mir_set = 0xffffffff;
-	regs->interrupts[1].mir_set = 0xffffffff;
-	regs->interrupts[2].mir_set = 0xffffffff;
-}
-
-static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs)
-{
-	return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
-}
-
-static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs)
-{
-	regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG;
-}
-
-static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs)
-{
-	regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG;
-}
-
-static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum)
-{
-	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
-	const unsigned set = inum / 32;
-	const unsigned pos = inum % 32;
-	regs->interrupts[set].mir_clear = (1 << pos);
-}
-
-static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum)
-{
-	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
-	const unsigned set = inum / 32;
-	const unsigned pos = inum % 32;
-	regs->interrupts[set].mir_set = (1 << pos);
-}
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,459 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AMDM37x on-chip interrupt controller driver.
- */
-
-#ifndef KERN_AMDM37x_UART_H_
-#define KERN_AMDM37x_UART_H_
-
-#include <typedefs.h>
-#include <console/chardev.h>
-#include <ddi/irq.h>
-
-/* AMDM37x TRM p. 2950 */
-#define AMDM37x_UART1_BASE_ADDRESS   0x4806a000
-#define AMDM37x_UART1_SIZE   1024
-#define AMDM37x_UART1_IRQ   72 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART2_BASE_ADDRESS   0x4806b000
-#define AMDM37x_UART2_SIZE   1024
-#define AMDM37x_UART2_IRQ   73 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART3_BASE_ADDRESS   0x49020000
-#define AMDM37x_UART3_SIZE   1024
-#define AMDM37x_UART3_IRQ   74 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART4_BASE_ADDRESS   0x49042000
-#define AMDM37x_UART4_SIZE   1024
-#define AMDM37x_UART4_IRQ   80 /* AMDM37x TRM p. 2418 */
-
-typedef struct {
-	union {
-		/** Stores lower part of the 14-bit baud divisor */
-		ioport32_t dll;
-#define AMDM37x_UART_DLL_MASK   (0xff)
-
-		/** Receive holding register */
-		const ioport32_t rhr;
-#define AMDM37x_UART_RHR_MASK   (0xff)
-
-		/** Transmit holding register */
-		ioport32_t thr;
-#define AMDM37x_UART_THR_MASK   (0xff)
-	};
-
-	union {
-		/** Stores higher part of the 14-bit baud divisor */
-		ioport32_t dlh;
-#define AMDM37x_UART_DLH_MASK   (0x1f)
-
-		/** Interrupt enable registers */
-		ioport32_t ier;
-#define AMDM37x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_UART_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
-#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
-#define AMDM37x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
-#define AMDM37x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
-#define AMDM37x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
-
-#define AMDM37x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
-#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
-#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
-
-#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
-#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
-#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
-#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
-#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
-	};
-
-	union {
-		/** Interrupt identification register */
-		const ioport32_t iir;
-#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
-#define AMDM37x_UART_IIR_TYPE_MASK   (0x1f)
-#define AMDM37x_UART_IIR_TYPE_SHIFT   (1)
-#define AMDM37x_UART_IIR_FCR_MASK   (0x3)
-#define AMDM37x_UART_IIR_FCR_SHIFT   (6)
-
-#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
-#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
-#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
-
-#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
-#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
-#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
-#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
-#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
-
-		/** FIFO control register */
-		ioport32_t fcr;
-#define AMDM37x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
-#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
-#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
-#define AMDM37x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
-
-#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
-
-#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
-
-		/** Enhanced feature register */
-		ioport32_t efr;
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
-
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
-
-#define AMDM37x_UART_EFR_ENH_FLAG   (1 << 4)
-#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
-#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
-#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
-	};
-
-	/** Line control register */
-	ioport32_t lcr;
-#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
-#define AMDM37x_UART_LCR_NB_STOP_FLAG   (1 << 2)
-#define AMDM37x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
-#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
-#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
-#define AMDM37x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
-#define AMDM37x_UART_LCR_DIV_EN_FLAG   (1 << 7)
-
-
-	union {
-		/** Modem control register */
-		ioport32_t mcr;
-#define AMDM37x_UART_MCR_DTR_FLAG   (1 << 0)
-#define AMDM37x_UART_MCR_RTS_FLAG   (1 << 1)
-#define AMDM37x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
-#define AMDM37x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
-#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
-#define AMDM37x_UART_MCR_XON_EN_FLAG   (1 << 5)
-#define AMDM37x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
-
-		/** UART: XON1 char, IRDA: ADDR1 address */
-		ioport32_t xon1_addr1;
-#define AMDM37x_UART_XON1_ADDR1_MASK   (0xff)
-	};
-
-	union {
-		/** Line status register */
-		const ioport32_t lsr;
-#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_UART_LSR_RX_OE_FLAG   (1 << 1)
-#define AMDM37x_UART_LSR_RX_PE_FLAG   (1 << 2)
-#define AMDM37x_UART_LSR_RX_FE_FLAG   (1 << 3)
-#define AMDM37x_UART_LSR_RX_BI_FLAG   (1 << 4)
-#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
-#define AMDM37x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
-#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
-
-#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
-#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
-
-#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
-#define AMDM37x_IRDA_LSR_CRC_FLAG   (1 << 2)
-#define AMDM37x_IRDA_LSR_ABORT_FLAG   (1 << 3)
-#define AMDM37x_IRDA_LSR_FTL_FLAG   (1 << 4)
-#define AMDM37x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
-#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
-#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
-
-		/** UART: XON2 char, IRDA: ADDR2 address */
-		ioport32_t xon2_addr2;
-	};
-
-	union {
-		/** Modem status register */
-		const ioport32_t msr;
-#define AMDM37x_UART_MSR_CTS_STS_FLAG   (1 << 0)
-#define AMDM37x_UART_MSR_DSR_STS_FLAG   (1 << 1)
-#define AMDM37x_UART_MSR_RI_STS_FLAG   (1 << 2)
-#define AMDM37x_UART_MSR_DCD_STS_FLAG   (1 << 3)
-#define AMDM37x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
-#define AMDM37x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
-#define AMDM37x_UART_MSR_NRI_STS_FLAG   (1 << 6)
-#define AMDM37x_UART_MSR_NCD_STS_FLAG   (1 << 7)
-
-		/** Transmission control register */
-		ioport32_t tcr;
-#define AMDM37x_UART_TCR_FIFO_TRIG_MASK   (0xf)
-#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
-#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
-
-		/** UART: XOFF1 char */
-		ioport32_t xoff1;
-#define AMDM37x_UART_XOFF1_MASK   (0xff)
-	};
-
-	union {
-		/* Scratchpad register, does nothing */
-		ioport32_t spr;
-#define AMDM37x_UART_SPR_MASK   (0xff)
-
-		/* Trigger level register */
-		ioport32_t tlr;
-#define AMDM37x_UART_TLR_LEVEL_MASK   (0xf)
-#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
-#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
-
-		/** UART: XOFF2 char */
-		ioport32_t xoff2;
-#define AMDM37x_UART_XOFF2_MASK   (0xff)
-	};
-
-	/** Mode definition register. */
-	ioport32_t mdr1;
-#define AMDM37x_UART_MDR_MS_MASK   (0x7)
-#define AMDM37x_UART_MDR_MS_SHIFT   (0)
-#define AMDM37x_UART_MDR_MS_UART16   (0x0)
-#define AMDM37x_UART_MDR_MS_SIR   (0x1)
-#define AMDM37x_UART_MDR_MS_UART16_AUTO   (0x2)
-#define AMDM37x_UART_MDR_MS_UART13   (0x3)
-#define AMDM37x_UART_MDR_MS_MIR   (0x4)
-#define AMDM37x_UART_MDR_MS_FIR   (0x5)
-#define AMDM37x_UART_MDR_MS_CIR   (0x6)
-#define AMDM37x_UART_MDR_MS_DISABLE   (0x7)
-
-#define AMDM37x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
-#define AMDM37x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
-#define AMDM37x_UART_MDR_SCT_FLAG   (1 << 5)
-#define AMDM37x_UART_MDR_SIP_FLAG   (1 << 6)
-#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
-
-	/** Mode definition register */
-	ioport32_t mdr2;
-#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
-#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
-#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
-#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
-#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
-#define AMDM37x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
-
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO line status register (IrDA only) */
-		const ioport32_t sflsr;
-#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
-#define AMDM37x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
-#define AMDM37x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
-#define AMDM37x_IRDA_SFLSR_OE_FLAG   (1 << 4)
-
-		/** Transmit frame length low (IrDA only) */
-		ioport32_t txfll;
-#define AMDM37x_UART_TXFLL_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Dummy register to restart TX or RX (IrDA only) */
-		const ioport32_t resume;
-		/** Transmit frame length high (IrDA only) */
-		ioport32_t txflh;
-#define AMDM37x_UART_TXFLH_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO register low (IrDA only) */
-		const ioport32_t sfregl;
-#define AMDM37x_UART_SFREGL_MASK   (0xff)
-		/** Received frame length low (IrDA only) */
-		ioport32_t rxfll;
-#define AMDM37x_UART_RXFLL_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO register high (IrDA only) */
-		const ioport32_t sfregh;
-#define AMDM37x_UART_SFREGH_MASK   (0xf)
-		/** Received frame length high (IrDA only) */
-		ioport32_t rxflh;
-#define AMDM37x_UART_RXFLH_MASK   (0xf)
-	};
-
-	union {
-		/** UART autobauding status register */
-		const ioport32_t uasr;
-#define AMDM37x_UART_UASR_SPEED_MASK   (0x1f)
-#define AMDM37x_UART_UASR_SPEED_SHIFT   (0)
-#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
-#define AMDM37x_UART_UASR_PARITY_MASK   (0x3)
-#define AMDM37x_UART_UASR_PARITY_SHIFT   (6)
-
-		/** BOF control register (IrDA only) */
-		ioport32_t blr; /* UART3 sepcific */
-#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
-#define AMDM37x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
-	};
-
-	/** Auxiliary control register (IrDA only) */
-	ioport32_t acreg; /* UART3 specific */
-#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
-#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
-#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
-#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
-#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
-#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
-#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
-#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
-
-	/** Supplementary control register */
-	ioport32_t scr;
-#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
-#define AMDM37x_UART_SCR_DMA_MODE_MASK   (0x3)
-#define AMDM37x_UART_SCR_DMA_MODE_SHIFT   (1)
-#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
-#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
-#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
-#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
-
-	/** Supplementary status register */
-	const ioport32_t ssr;
-#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
-#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
-#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
-
-	/** BOF Length register (IrDA only)*/
-	ioport32_t eblr; /* UART3 specific */
-#define AMDM37x_IRDA_EBLR_DISABLED   (0x00)
-#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
-
-	uint32_t padd0_;
-
-	/** Module version register */
-	const ioport32_t mvr;
-#define AMDM37x_UART_MVR_MINOR_MASK   (0xf)
-#define AMDM37x_UART_MVR_MINOR_SHIFT   (0)
-#define AMDM37x_UART_MVR_MAJOR_MASK   (0xf)
-#define AMDM37x_UART_MVR_MAJOR_SHIFT   (4)
-
-	/** System configuration register */
-	ioport32_t sysc;
-#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
-#define AMDM37x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
-#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
-#define AMDM37x_UART_SYSC_IDLE_MODE_MASK   (0x3)
-#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT   (3)
-#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
-#define AMDM37x_UART_SYSC_IDLE_MODE_NO   (0x1)
-#define AMDM37x_UART_SYSC_IDLE_MODE_SMART   (0x2)
-
-	/** System status register */
-	const ioport32_t syss;
-#define AMDM37x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
-
-	/** Wake-up enable register */
-	ioport32_t wer;
-#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
-#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
-#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
-#define AMDM37x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
-#define AMDM37x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
-#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
-
-	/** Carrier frequency prescaler */
-	ioport32_t cfps;	/* UART3 specific */
-#define AMDM37x_UART_CFPS_MASK   (0xff)
-
-	/** Number of bytes in RX fifo */
-	const ioport32_t rx_fifo_lvl;
-#define AMDM37x_UART_RX_FIFO_LVL_MASK   (0xff)
-
-	/** Number of bytes in TX fifo */
-	const ioport32_t tx_fifo_lvl;
-#define AMDM37x_UART_TX_FIFO_LVL_MASK   (0xff)
-
-	/** RX/TX empty interrupts */
-	ioport32_t ier2;
-#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
-#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
-
-	/** RX/TX empty status */
-	ioport32_t isr2;
-#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
-#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
-
-	uint32_t padd2_[3];
-
-	/** Mode definition register 3 */
-	ioport32_t mdr3;
-#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
-} amdm37x_uart_regs_t;
-
-typedef struct {
-	amdm37x_uart_regs_t *regs;
-	indev_t *indev;
-	outdev_t outdev;
-	irq_t irq;
-} amdm37x_uart_t;
-
-
-bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t);
-void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *);
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
===================================================================
--- kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,163 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AMDM37x on-chip uart serial line driver.
- */
-
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
-#include <ddi/device.h>
-#include <str.h>
-#include <mm/km.h>
-
-static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b)
-{
-	/* Wait for buffer */
-	while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG);
-	/* Write to the outgoing fifo */
-	uart->regs->thr = b;
-}
-
-static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch)
-{
-	amdm37x_uart_t *uart = dev->data;
-	if (!ascii_check(ch)) {
-		amdm37x_uart_txb(uart, U_SPECIAL);
-	} else {
-		if (ch == '\n')
-			amdm37x_uart_txb(uart, '\r');
-		amdm37x_uart_txb(uart, ch);
-	}
-}
-
-static outdev_operations_t amdm37x_uart_ops = {
-	.redraw = NULL,
-	.write = amdm37x_uart_putchar,
-};
-
-static irq_ownership_t amdm37x_uart_claim(irq_t *irq)
-{
-	return IRQ_ACCEPT;
-}
-
-static void amdm37x_uart_handler(irq_t *irq)
-{
-	amdm37x_uart_t *uart = irq->instance;
-	while ((uart->regs->rx_fifo_lvl)) {
-		const uint8_t val = uart->regs->rhr;
-		if (uart->indev && val) {
-			indev_push_character(uart->indev, val);
-		}
-	}
-}
-
-bool amdm37x_uart_init(
-    amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
-{
-	ASSERT(uart);
-	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
-
-	ASSERT(uart->regs);
-
-	/* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */
-#if 0
-	/* Soft reset the port */
-	uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
-	while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
-#endif
-
-	/* Enable access to EFR register */
-	const uint8_t lcr = uart->regs->lcr; /* Save old value */
-	uart->regs->lcr = 0xbf;              /* Sets config mode B */
-
-	/* Enable access to TCL_TLR register */
-	const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG;
-	uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */
-	uart->regs->lcr = 0x80;              /* Config mode A */
-
-	/* Set default (val 0) triggers, disable DMA enable FIFOs */
-	const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
-	/* Enable access to tcr and tlr registers */
-	uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
-
-	/* Enable FIFOs */
-	uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
-
-	/* Eneble fine granularity for RX FIFO and set trigger level to 1,
-	 * TX FIFO, trigger level is irelevant*/
-	uart->regs->lcr = 0xbf;              /* Sets config mode B */
-	uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
-	uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
-
-	/* Restore enhanced */
-	if (!enhanced)
-		uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG;
-
-	uart->regs->lcr = 0x80;              /* Config mode A */
-	/* Restore tcl_lcr access flag*/
-	if (!tcl_tlr)
-		uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
-
-	/* Restore lcr */
-	uart->regs->lcr = lcr;
-
-	/* Disable interrupts */
-	uart->regs->ier = 0;
-
-	/* Setup outdev */
-	outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
-	uart->outdev.data = uart;
-
-	/* Initialize IRQ */
-	irq_initialize(&uart->irq);
-	uart->irq.devno = device_assign_devno();
-	uart->irq.inr = interrupt;
-	uart->irq.claim = amdm37x_uart_claim;
-	uart->irq.handler = amdm37x_uart_handler;
-	uart->irq.instance = uart;
-
-	return true;
-}
-
-void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev)
-{
-	ASSERT(uart);
-	/* Set indev */
-	uart->indev = indev;
-	/* Register interrupt. */
-	irq_register(&uart->irq);
-	/* Enable interrupt on receive */
-	uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
-}
-
-/**
- * @}
- */
Index: tools/mkuimage.py
===================================================================
--- tools/mkuimage.py	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ tools/mkuimage.py	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -120,5 +120,5 @@
 	header.start_addr = start_addr	# Address of entry point
 	header.data_crc = data_crc
-	header.os = 2			# NetBSD
+	header.os = 5			# Linux
 	header.arch = 2			# ARM
 	header.img_type = 2		# Kernel
Index: uspace/Makefile
===================================================================
--- uspace/Makefile	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ uspace/Makefile	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -174,9 +174,4 @@
 endif
 
-ifeq ($(UARCH),arm32)
-	DIRS += \
-		drv/infrastructure/rootamdm37x
-endif
-
 ## System libraries
 #
Index: uspace/drv/bus/usb/ehci/ehci.ma
===================================================================
--- uspace/drv/bus/usb/ehci/ehci.ma	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ uspace/drv/bus/usb/ehci/ehci.ma	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -1,2 +1,1 @@
-20 usb/host=ehci
 10 pci/class=0c&subclass=03&progif=20
Index: uspace/drv/bus/usb/ohci/ohci.ma
===================================================================
--- uspace/drv/bus/usb/ohci/ohci.ma	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ uspace/drv/bus/usb/ohci/ohci.ma	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -1,2 +1,1 @@
-20 usb/host=ohci
 10 pci/class=0c&subclass=03&progif=10
Index: uspace/drv/bus/usb/ohci/ohci_regs.h
===================================================================
--- uspace/drv/bus/usb/ohci/ohci_regs.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ uspace/drv/bus/usb/ohci/ohci_regs.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -228,5 +228,5 @@
 #define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
 #define RHPS_CHANGE_WC_MASK 0x1f0000
-} ohci_regs_t;
+} __attribute__((packed)) ohci_regs_t;
 #endif
 /**
Index: pace/drv/infrastructure/rootamdm37x/Makefile
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/Makefile	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,37 +1,0 @@
-#
-# Copyright (c) 2012 Jan Vesely
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# - Redistributions of source code must retain the above copyright
-#   notice, this list of conditions and the following disclaimer.
-# - Redistributions in binary form must reproduce the above copyright
-#   notice, this list of conditions and the following disclaimer in the
-#   documentation and/or other materials provided with the distribution.
-# - The name of the author may not be used to endorse or promote products
-#   derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-
-USPACE_PREFIX = ../../..
-LIBS = $(LIBDRV_PREFIX)/libdrv.a
-EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include
-BINARY = rootamdm37x
-
-SOURCES = \
-	rootamdm37x.c
-
-include $(USPACE_PREFIX)/Makefile.common
Index: pace/drv/infrastructure/rootamdm37x/core_cm.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/core_cm.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,193 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup amdm37xdrvcorecm
- * @{
- */
-/** @file
- * @brief CORE Clock Management IO register structure.
- */
-#ifndef AMDM37x_CORE_CM_H
-#define AMDM37x_CORE_CM_H
-#include <sys/types.h>
-
-/* AM/DM37x TRM p.447 */
-#define CORE_CM_BASE_ADDRESS  0x48004a00
-#define CORE_CM_SIZE  8192
-
-typedef struct {
-	ioport32_t fclken1;
-#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG  (1 << 9)
-#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG  (1 << 10)
-#define CORE_CM_FCLKEN1_EN_GPT10_FLAG  (1 << 11)
-#define CORE_CM_FCLKEN1_EN_GPT11_FLAG  (1 << 12)
-#define CORE_CM_FCLKEN1_EN_UART1_FLAG  (1 << 13)
-#define CORE_CM_FCLKEN1_EN_UART2_FLAG  (1 << 14)
-#define CORE_CM_FCLKEN1_EN_I2C1_FLAG  (1 << 15)
-#define CORE_CM_FCLKEN1_EN_I2C2_FLAG  (1 << 16)
-#define CORE_CM_FCLKEN1_EN_I2C3_FLAG  (1 << 17)
-#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG  (1 << 18)
-#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG  (1 << 19)
-#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG  (1 << 20)
-#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG  (1 << 21)
-#define CORE_CM_FCLKEN1_EN_HDQ_FLAG  (1 << 22)
-#define CORE_CM_FCLKEN1_EN_MMC1_FLAG  (1 << 24)
-#define CORE_CM_FCLKEN1_EN_MMC2_FLAG  (1 << 25)
-#define CORE_CM_FCLKEN1_EN_MMC3_FLAG  (1 << 30)
-
-	uint32_t padd0_;
-	ioport32_t fclken3;
-#define CORE_CM_FCLKEN3_EN_TS_FLAG  (1 << 1)
-#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG  (1 << 2)
-
-	uint32_t padd1_;
-	ioport32_t iclken1;
-#define CORE_CM_ICLKEN1_EN_SDRC_FLAG  (1 << 1)
-#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG  (1 << 4)
-#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG  (1 << 6)
-#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG  (1 << 7)
-#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG  (1 << 9)
-#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG  (1 << 10)
-#define CORE_CM_ICLKEN1_EN_GPT10_FLAG  (1 << 11)
-#define CORE_CM_ICLKEN1_EN_GPT11_FLAG  (1 << 12)
-#define CORE_CM_ICLKEN1_EN_UART1_FLAG  (1 << 13)
-#define CORE_CM_ICLKEN1_EN_UART2_FLAG  (1 << 14)
-#define CORE_CM_ICLKEN1_EN_I2C1_FLAG  (1 << 15)
-#define CORE_CM_ICLKEN1_EN_I2C2_FLAG  (1 << 16)
-#define CORE_CM_ICLKEN1_EN_I2C3_FLAG  (1 << 17)
-#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG  (1 << 18)
-#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG  (1 << 19)
-#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG  (1 << 20)
-#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG  (1 << 21)
-#define CORE_CM_ICLKEN1_EN_HDQ_FLAG  (1 << 22)
-#define CORE_CM_ICLKEN1_EN_MMC1_FLAG  (1 << 24)
-#define CORE_CM_ICLKEN1_EN_MMC2_FLAG  (1 << 25)
-#define CORE_CM_ICLKEN1_EN_ICR_FLAG  (1 << 29)
-#define CORE_CM_ICLKEN1_EN_MMC3_FLAG  (1 << 30)
-
-	ioport32_t reserved1;
-	ioport32_t iclken3;
-#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG  (1 << 2)
-
-	uint32_t padd2_;
-	const ioport32_t idlest1;
-#define CORE_CM_IDLEST1_ST_SDRC_FLAG  (1 << 1)
-#define CORE_CM_IDLEST1_ST_SDMA_FLAG  (1 << 2)
-#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG  (1 << 4)
-#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG  (1 << 5)
-#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG  (1 << 6)
-#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG  (1 << 7)
-#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG  (1 << 9)
-#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG  (1 << 10)
-#define CORE_CM_IDLEST1_ST_GPT10_FLAG  (1 << 11)
-#define CORE_CM_IDLEST1_ST_GPT11_FLAG  (1 << 12)
-#define CORE_CM_IDLEST1_ST_UART1_FLAG  (1 << 13)
-#define CORE_CM_IDLEST1_ST_UART2_FLAG  (1 << 14)
-#define CORE_CM_IDLEST1_ST_I2C1_FLAG  (1 << 15)
-#define CORE_CM_IDLEST1_ST_I2C2_FLAG  (1 << 16)
-#define CORE_CM_IDLEST1_ST_I2C3_FLAG  (1 << 17)
-#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG  (1 << 18)
-#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG  (1 << 19)
-#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG  (1 << 20)
-#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG  (1 << 21)
-#define CORE_CM_IDLEST1_ST_HDQ_FLAG  (1 << 22)
-#define CORE_CM_IDLEST1_ST_MMC1_FLAG  (1 << 24)
-#define CORE_CM_IDLEST1_ST_MMC2_FLAG  (1 << 25)
-#define CORE_CM_IDLEST1_ST_ICR_FLAG  (1 << 29)
-#define CORE_CM_IDLEST1_ST_MMC3_FLAG  (1 << 30)
-
-	const ioport32_t reserved2;
-	const ioport32_t idlest3;
-#define CORE_CM_IDLEST3_ST_USBTLL_FLAG  (1 << 2)
-
-	uint32_t padd3_;
-	ioport32_t autoidle1;
-#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG  (1 << 4)
-#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG  (1 << 6)
-#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG  (1 << 7)
-#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG  (1 << 9)
-#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG  (1 << 10)
-#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG  (1 << 11)
-#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG  (1 << 12)
-#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG  (1 << 13)
-#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG  (1 << 14)
-#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG  (1 << 15)
-#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG  (1 << 16)
-#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG  (1 << 17)
-#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG  (1 << 18)
-#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG  (1 << 19)
-#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG  (1 << 20)
-#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG  (1 << 21)
-#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG  (1 << 22)
-#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG  (1 << 24)
-#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG  (1 << 25)
-#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG  (1 << 29)
-#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG  (1 << 30)
-
-	ioport32_t reserved3;
-	ioport32_t autoidle3;
-#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG  (1 << 2)
-
-	uint32_t padd4_;
-	ioport32_t clksel;
-#define CORE_CM_CLKSEL_CLKSEL_L3_MASK  0x3
-#define CORE_CM_CLKSEL_CLKSEL_L3_SHIFT  0
-#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1  0x1
-#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2  0x2
-#define CORE_CM_CLKSEL_CLKSEL_L4_MASK  0x3
-#define CORE_CM_CLKSEL_CLKSEL_L4_SHIFT  2
-#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1  0x1
-#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2  0x2
-#define CORE_CM_CLKSEL_CLKSEL_96M_MASK  0x3
-#define CORE_CM_CLKSEL_CLKSEL_96M_SHIFT  2
-#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1  0x1
-#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2  0x2
-#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6)
-#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 6)
-
-	uint32_t padd5_;
-	ioport32_t clkstctrl;
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK  0x3
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_SHIFT  0
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN  0x0
-#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS  0x3
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK  0x3
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_SHIFT  2
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN  0x0
-#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS  0x3
-
-	const ioport32_t clkstst;
-#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG  (1 << 0)
-#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG  (1 << 1)
-
-} core_cm_regs_t;
-
-#endif
-/**
- * @}
- */
Index: pace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,371 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @defgroup root_amdm37x TI AM/DM37x platform driver.
- * @brief HelenOS TI AM/DM37x platform driver.
- * @{
- */
-
-/** @file
- */
-
-#include <ddf/driver.h>
-#include <ddf/log.h>
-#include <errno.h>
-#include <ops/hw_res.h>
-#include <stdio.h>
-#include <ddi.h>
-
-#include "uhh.h"
-#include "usbtll.h"
-#include "core_cm.h"
-#include "usbhost_cm.h"
-
-#define NAME  "rootamdm37x"
-
-/** Obtain function soft-state from DDF function node */
-#define ROOTARM_FUN(fnode) \
-	((rootamdm37x_fun_t *) (fnode)->driver_data)
-
-typedef struct {
-	hw_resource_list_t hw_resources;
-} rootamdm37x_fun_t;
-
-#define OHCI_BASE_ADDRESS  0x48064400
-#define OHCI_SIZE  1024
-#define EHCI_BASE_ADDRESS  0x48064800
-#define EHCI_SIZE  1024
-
-static hw_resource_t ohci_res[] = {
-	{
-		.type = MEM_RANGE,
-		/* See amdm37x TRM page. 3316 for these values */
-		.res.io_range = {
-			.address = OHCI_BASE_ADDRESS,
-			.size = OHCI_SIZE,
-			.endianness = LITTLE_ENDIAN
-		},
-	},
-	{
-		.type = INTERRUPT,
-		.res.interrupt = { .irq = 76 },
-	},
-};
-
-static const rootamdm37x_fun_t ohci = {
-	.hw_resources = {
-	    .resources = ohci_res,
-	    .count = sizeof(ohci_res)/sizeof(ohci_res[0]),
-	}
-};
-
-static hw_resource_t ehci_res[] = {
-	{
-		.type = MEM_RANGE,
-		/* See amdm37x TRM page. 3316 for these values */
-		.res.io_range = {
-			.address = EHCI_BASE_ADDRESS,
-			.size = EHCI_SIZE,
-			.endianness = LITTLE_ENDIAN
-		},
-	},
-	{
-		.type = INTERRUPT,
-		.res.interrupt = { .irq = 77 },
-	},
-};
-
-static const rootamdm37x_fun_t ehci = {
-	.hw_resources = {
-	    .resources = ehci_res,
-	    .count = sizeof(ehci_res)/sizeof(ehci_res[0]),
-	}
-};
-
-static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode);
-static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun);
-
-static hw_res_ops_t fun_hw_res_ops = {
-	.get_resource_list = &rootamdm37x_get_resources,
-	.enable_interrupt = &rootamdm37x_enable_interrupt,
-};
-
-static ddf_dev_ops_t rootamdm37x_fun_ops =
-{
-	.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops
-};
-
-static int usb_clocks(bool on)
-{
-	usbhost_cm_regs_t *usb_host_cm = NULL;
-	core_cm_regs_t *l4_core_cm = NULL;
-
-	int ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
-	    (void**)&usb_host_cm);
-	if (ret != EOK)
-		return ret;
-
-	ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
-	    (void**)&l4_core_cm);
-	if (ret != EOK)
-		return ret;
-
-	assert(l4_core_cm);
-	assert(usb_host_cm);
-	if (on) {
-		l4_core_cm->iclken3 |= CORE_CM_ICLKEN3_EN_USBTLL_FLAG;
-		l4_core_cm->fclken3 |= CORE_CM_FCLKEN3_EN_USBTLL_FLAG;
-		usb_host_cm->iclken |= USBHOST_CM_ICLKEN_EN_USBHOST;
-		usb_host_cm->fclken |= USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG;
-		usb_host_cm->fclken |= USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG;
-	} else {
-		usb_host_cm->fclken &= ~USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG;
-		usb_host_cm->fclken &= ~USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG;
-		usb_host_cm->iclken &= ~USBHOST_CM_ICLKEN_EN_USBHOST;
-		l4_core_cm->fclken3 &= ~CORE_CM_FCLKEN3_EN_USBTLL_FLAG;
-		l4_core_cm->iclken3 &= ~CORE_CM_ICLKEN3_EN_USBTLL_FLAG;
-	}
-
-	//TODO Unmap those registers.
-
-	return ret;
-}
-
-/** Initialize USB TLL port connections.
- *
- * Different modes are on page 3312 of the Manual Figure 22-34.
- * Select mode than can operate in FS/LS.
- */
-static int usb_tll_init()
-{
-	tll_regs_t *usb_tll = NULL;
-	uhh_regs_t *uhh_conf = NULL;
-
-	int ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS,
-	    AMDM37x_USBTLL_SIZE, (void**)&usb_tll);
-	if (ret != EOK)
-		return ret;
-
-	ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS,
-	    AMDM37x_UHH_SIZE, (void**)&uhh_conf);
-	if (ret != EOK)
-		return ret;
-
-	/* Reset USB TLL */
-	usb_tll->sysconfig |= TLL_SYSCONFIG_SOFTRESET_FLAG;
-	ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
-	while (!(usb_tll->sysstatus & TLL_SYSSTATUS_RESET_DONE_FLAG));
-	ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
-
-	{
-	/* Setup idle mode (smart idle) */
-	uint32_t sysc = usb_tll->sysconfig;
-	sysc |= TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG;
-	sysc = (sysc
-	    & ~(TLL_SYSCONFIG_SIDLE_MODE_MASK << TLL_SYSCONFIG_SIDLE_MODE_SHIFT)
-	    ) | (0x2 << TLL_SYSCONFIG_SIDLE_MODE_SHIFT);
-	usb_tll->sysconfig = sysc;
-	ddf_msg(LVL_DEBUG2, "Set TLL->sysconfig (%p) to %x:%x.",
-	    &usb_tll->sysconfig, usb_tll->sysconfig, sysc);
-	}
-
-	{
-	/* Smart idle for UHH */
-	uint32_t sysc = uhh_conf->sysconfig;
-	sysc |= UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG;
-	sysc = (sysc
-	    & ~(UHH_SYSCONFIG_SIDLE_MODE_MASK << UHH_SYSCONFIG_SIDLE_MODE_SHIFT)
-	    ) | (0x2 << UHH_SYSCONFIG_SIDLE_MODE_SHIFT);
-	sysc = (sysc
-	    & ~(UHH_SYSCONFIG_MIDLE_MODE_MASK << UHH_SYSCONFIG_MIDLE_MODE_SHIFT)
-	    ) | (0x2 << UHH_SYSCONFIG_MIDLE_MODE_SHIFT);
-	ddf_msg(LVL_DEBUG2, "Set UHH->sysconfig (%p) to %x.",
-	    &uhh_conf->sysconfig, uhh_conf->sysconfig);
-	uhh_conf->sysconfig = sysc;
-
-	/* All ports are connected on BBxM */
-	uhh_conf->hostconfig |= (UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG
-	    | UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG
-	    | UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG);
-
-	/* Set all ports to go through TLL(UTMI)
-	 * Direct connection can only work in HS mode */
-	uhh_conf->hostconfig |= (UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG
-	    | UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG
-	    | UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG);
-	ddf_msg(LVL_DEBUG2, "Set UHH->hostconfig (%p) to %x.",
-	    &uhh_conf->hostconfig, uhh_conf->hostconfig);
-	}
-
-	usb_tll->shared_conf |= TLL_SHARED_CONF_FCLK_IS_ON_FLAG;
-	ddf_msg(LVL_DEBUG2, "Set shared conf port (%p) to %x.",
-	    &usb_tll->shared_conf, usb_tll->shared_conf);
-
-	for (unsigned i = 0; i < 3; ++i) {
-		uint32_t ch = usb_tll->channel_conf[i];
-		/* Clear Channel mode and FSLS mode */
-		ch &= ~(TLL_CHANNEL_CONF_CHANMODE_MASK
-		    << TLL_CHANNEL_CONF_CHANMODE_SHIFT)
-		    & ~(TLL_CHANNEL_CONF_FSLSMODE_MASK
-		    << TLL_CHANNEL_CONF_FSLSMODE_SHIFT);
-
-		/* Serial mode is the only one capable of FS/LS operation. */
-		ch |= (TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE
-		    << TLL_CHANNEL_CONF_CHANMODE_SHIFT);
-
-		/* Select FS/LS mode, no idea what the difference is
-		 * one of bidirectional modes might be good choice
-		 * 2 = 3pin bidi phy. */
-		ch |= (2 << TLL_CHANNEL_CONF_FSLSMODE_SHIFT);
-
-		/* Write to register */
-		ddf_msg(LVL_DEBUG2, "Setting port %u(%p) to %x.",
-		    i, &usb_tll->channel_conf[i], ch);
-		usb_tll->channel_conf[i] = ch;
-	}
-	return EOK;
-}
-
-static bool rootamdm37x_add_fun(ddf_dev_t *dev, const char *name,
-    const char *str_match_id, const rootamdm37x_fun_t *fun)
-{
-	ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name);
-	
-	ddf_fun_t *fnode = NULL;
-	match_id_t *match_id = NULL;
-	
-	/* Create new device. */
-	fnode = ddf_fun_create(dev, fun_inner, name);
-	if (fnode == NULL)
-		goto failure;
-	
-	fnode->driver_data = (void*)fun;
-	
-	/* Initialize match id list */
-	match_id = create_match_id();
-	if (match_id == NULL)
-		goto failure;
-	
-	match_id->id = str_match_id;
-	match_id->score = 100;
-	add_match_id(&fnode->match_ids, match_id);
-	
-	/* Set provided operations to the device. */
-	fnode->ops = &rootamdm37x_fun_ops;
-	
-	/* Register function. */
-	if (ddf_fun_bind(fnode) != EOK) {
-		ddf_msg(LVL_ERROR, "Failed binding function %s.", name);
-		goto failure;
-	}
-	
-	return true;
-	
-failure:
-	if (match_id != NULL)
-		match_id->id = NULL;
-	
-	if (fnode != NULL) {
-		fnode->driver_data = NULL;
-		ddf_fun_destroy(fnode);
-	}
-	
-	ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name);
-	
-	return false;
-}
-
-/** Add the root device.
- *
- * @param dev Device which is root of the whole device tree
- *            (both of HW and pseudo devices).
- *
- * @return Zero on success, negative error number otherwise.
- *
- */
-static int rootamdm37x_dev_add(ddf_dev_t *dev)
-{
-	int ret = usb_clocks(true);
-	if (ret != EOK) {
-		ddf_msg(LVL_FATAL, "Failed to enable USB HC clocks!.\n");
-		return ret;
-	}
-
-	ret = usb_tll_init();
-	if (ret != EOK) {
-		ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n");
-		usb_clocks(false);
-		return ret;
-	}
-
-	/* Register functions */
-	if (!rootamdm37x_add_fun(dev, "ohci", "usb/host=ohci", &ohci))
-		ddf_msg(LVL_ERROR, "Failed to add OHCI function for "
-		    "BeagleBoard-xM platform.");
-	if (!rootamdm37x_add_fun(dev, "ehci", "usb/host=ehci", &ehci))
-		ddf_msg(LVL_ERROR, "Failed to add EHCI function for "
-		    "BeagleBoard-xM platform.");
-
-	return EOK;
-}
-
-/** The root device driver's standard operations. */
-static driver_ops_t rootamdm37x_ops = {
-	.dev_add = &rootamdm37x_dev_add
-};
-
-/** The root device driver structure. */
-static driver_t rootamdm37x_driver = {
-	.name = NAME,
-	.driver_ops = &rootamdm37x_ops
-};
-
-static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode)
-{
-	rootamdm37x_fun_t *fun = ROOTARM_FUN(fnode);
-	assert(fun != NULL);
-	return &fun->hw_resources;
-}
-
-static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun)
-{
-	/* TODO */
-	return false;
-}
-
-int main(int argc, char *argv[])
-{
-	printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME);
-	ddf_log_init(NAME, LVL_ERROR);
-	return ddf_driver_main(&rootamdm37x_driver);
-}
-
-/**
- * @}
- */
Index: pace/drv/infrastructure/rootamdm37x/rootamdm37x.ma
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,1 +1,0 @@
-10 platform/beagleboardxm
Index: pace/drv/infrastructure/rootamdm37x/uhh.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/uhh.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,93 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup amdm37xdrvuhh
- * @{
- */
-/** @file
- * @brief UHH IO register structure.
- */
-#ifndef AMDM37x_UHH_H
-#define AMDM37x_UHH_H
-#include <sys/types.h>
-
-#define AMDM37x_UHH_BASE_ADDRESS  0x48064000
-#define AMDM37x_UHH_SIZE  1024
-
-typedef struct {
-	const ioport32_t revision;
-#define UHH_REVISION_MASK  0xf
-#define UHH_REVISION_MINOR_SHIFT  0
-#define UHH_REVISION_MAJOR_SHIFT  4
-
-	uint32_t padd0_[3];
-	ioport32_t sysconfig;
-#define UHH_SYSCONFIG_AUTOIDLE_FLAG  (1 << 0)
-#define UHH_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
-#define UHH_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
-#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG  (1 << 8)
-#define UHH_SYSCONFIG_SIDLE_MODE_MASK  0x3
-#define UHH_SYSCONFIG_SIDLE_MODE_SHIFT  3
-#define UHH_SYSCONFIG_MIDLE_MODE_MASK  0x3
-#define UHH_SYSCONFIG_MIDLE_MODE_SHIFT  12
-
-	const ioport32_t sysstatus;
-#define UHH_SYSSTATUS_RESETDONE_FLAG  (1 << 0)
-#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG  (1 << 1)
-#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG  (1 << 2)
-
-	uint32_t padd1_[10];
-	ioport32_t hostconfig;
-#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG  (1 << 0)
-#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG  (1 << 1)
-#define UHH_HOSTCONFIG_ENA_INCR4_FLAG  (1 << 2)
-#define UHH_HOSTCONFIG_ENA_INCR8_FLAG  (1 << 3)
-#define UHH_HOSTCONFIG_ENA_INCR16_FLA  (1 << 4)
-#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG  (1 << 5)
-#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG  (1 << 8)
-#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG  (1 << 9)
-#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG  (1 << 10)
-#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG  (1 << 11)
-#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG  (1 << 12)
-
-	ioport32_t debug_csr;
-#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK  (0x3f)
-#define UHH_DEBUG_CSR_EHCI_FLADJ_SHIFT  0
-#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG  (1 << 6)
-#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG  (1 << 7)
-#define UHH_DEBUG_CSR_OHCI_GLOBAL_sUSPEND_FLAG  (1 << 16)
-#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG  (1 << 17)
-#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG  (1 << 18)
-#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG  (1 << 19)
-
-} uhh_regs_t;
-
-#endif
-/**
- * @}
- */
Index: pace/drv/infrastructure/rootamdm37x/usbhost_cm.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/usbhost_cm.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,82 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup amdm37xdrvusbhostcm
- * @{
- */
-/** @file
- * @brief USBHOST Clock Management IO register structure.
- */
-#ifndef AMDM37x_USBHOST_CM_H
-#define AMDM37x_USBHOST_CM_H
-#include <sys/types.h>
-
-/* AM/DM37x TRM p.447 */
-#define USBHOST_CM_BASE_ADDRESS  0x48005400
-#define USBHOST_CM_SIZE  8192
-
-typedef struct {
-	ioport32_t fclken;
-#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG  (1 << 0)
-#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG  (1 << 1)
-
-	uint32_t padd0_[3];
-	ioport32_t iclken;
-#define USBHOST_CM_ICLKEN_EN_USBHOST  (1 << 0)
-
-	uint32_t padd1_[3];
-	const ioport32_t idlest;
-#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG  (1 << 0)
-#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG  (1 << 1)
-
-	uint32_t padd2_[3];
-	ioport32_t autoidle;
-#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG  (1 << 0)
-
-	uint32_t padd3_[4];
-	ioport32_t sleepdep;
-#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG  (1 << 1)
-#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG  (1 << 2)
-
-	ioport32_t clkstctrl;
-#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK  0x3
-#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SHIFT  0
-#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS  0x0
-#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP  0x1
-#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP  0x2
-#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN  0x1
-
-	ioport32_t clkstst;
-#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST  (1 << 0)
-} usbhost_cm_regs_t;
-
-#endif
-/**
- * @}
- */
-
Index: pace/drv/infrastructure/rootamdm37x/usbtll.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/usbtll.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ 	(revision )
@@ -1,115 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/** @addtogroup amdm37xdrvusbtll
- * @{
- */
-/** @file
- * @brief USBTLL IO register structure.
- */
-#ifndef AMDM37x_USBTLL_H
-#define AMDM37x_USBTLL_H
-#include <sys/types.h>
-
-#define AMDM37x_USBTLL_BASE_ADDRESS  0x48062000
-#define AMDM37x_USBTLL_SIZE  4096
-
-typedef struct {
-	const ioport32_t revision;
-#define TLL_REVISION_MASK  0xf
-#define TLL_REVISION_MINOR_SHIFT  0
-#define TLL_REVISION_MAJOR_SHIFT  4
-
-	uint32_t padd0_[3];
-	ioport32_t sysconfig;
-#define TLL_SYSCONFIG_AUTOIDLE_FLAG  (1 << 0)
-#define TLL_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
-#define TLL_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
-#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG  (1 << 8)
-#define TLL_SYSCONFIG_SIDLE_MODE_MASK  0x3
-#define TLL_SYSCONFIG_SIDLE_MODE_SHIFT  3
-
-	ioport32_t sysstatus;
-#define TLL_SYSSTATUS_RESET_DONE_FLAG  (1 << 0)
-
-	const ioport32_t irqstatus;
-#define TLL_IRQSTATUS_FCLK_START_FLAG  (1 << 0)
-#define TLL_IRQSTATUS_FCLK_END_FLAG  (1 << 1)
-#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG  (1 << 2)
-
-	ioport32_t irqenable;
-#define TLL_IRQSTATUS_FCLK_START_EN_FLAG  (1 << 0)
-#define TLL_IRQSTATUS_FCLK_END_EN_FLAG  (1 << 1)
-#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG  (1 << 2)
-
-	uint32_t padd1_[4];
-	ioport32_t shared_conf;
-#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG  (1 << 0)
-#define TLL_SHARED_CONF_FCLK_REQ_FLAG  (1 << 1)
-#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG  (1 << 5)
-#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG  (1 << 6)
-#define TLL_SHARED_CONF_USB_DIVRATIO_MASK  0x7
-#define TLL_SHARED_CONF_USB_DIVRATIO_SHIFT 2
-
-	uint32_t padd2_[3];
-	ioport32_t channel_conf[3];
-#define TLL_CHANNEL_CONF_CHANEN_FLAG  (1 << 0)
-#define TLL_CHANNEL_CONF_CHANMODE_MASK  0x3
-#define TLL_CHANNEL_CONF_CHANMODE_SHIFT  1
-#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE 0
-#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE 1
-#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE 2
-#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE 3
-#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG  (1 << 3)
-#define TLL_CHANNEL_CONF_TLLATTACH_FLAG  (1 << 4)
-#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG  (1 << 5)
-#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG  (1 << 6)
-#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG  (1 << 7)
-#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG  (1 << 8)
-#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG  (1 << 9)
-#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG  (1 << 10)
-#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG  (1 << 11)
-#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG  (1 << 15)
-#define TLL_CHANNEL_CONF_DRVVBUS_FLAG  (1 << 16)
-#define TLL_CHANNEL_CONF_TESTEN_FLAG  (1 << 17)
-#define TLL_CHANNEL_CONF_TESTTXEN_FLAG  (1 << 18)
-#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG  (1 << 19)
-#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG  (1 << 20)
-#define TLL_CHANNEL_CONF_FSLSMODE_MASK  0xf
-#define TLL_CHANNEL_CONF_FSLSMODE_SHIFT  24
-#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK  0x3
-#define TLL_CHANNEL_CONF_FSLSLINESTATE_SHIFT  28
-
-	/* The rest are 8bit ULPI registers */
-} tll_regs_t;
-
-#endif
-/**
- * @}
- */
-
Index: uspace/lib/usbdev/include/usb/dev/request.h
===================================================================
--- uspace/lib/usbdev/include/usb/dev/request.h	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ uspace/lib/usbdev/include/usb/dev/request.h	(revision d11a1811118ec8e5eb8ca4beae291275a4ce36b6)
@@ -93,8 +93,8 @@
 	uint8_t request;
 	/** Main parameter to the request. */
-	union __attribute__ ((packed)) {
+	union {
 		uint16_t value;
 		/* FIXME: add #ifdefs according to host endianness */
-		struct __attribute__ ((packed)) {
+		struct {
 			uint8_t value_low;
 			uint8_t value_high;
@@ -108,6 +108,4 @@
 	uint16_t length;
 } __attribute__ ((packed)) usb_device_request_setup_packet_t;
-
-int assert[(sizeof(usb_device_request_setup_packet_t) == 8) ? 1: -1];
 
 int usb_control_request_set(usb_pipe_t *,
