Changeset ce6e001 in mainline for uspace/drv/bus/usb/xhci/hw_struct/regs.h
- Timestamp:
- 2017-06-15T21:31:09Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 62ba2cbe
- Parents:
- 48197c1
- File:
-
- 1 edited
-
uspace/drv/bus/usb/xhci/hw_struct/regs.h (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/hw_struct/regs.h
r48197c1 rce6e001 114 114 pio_clear_##size((ptr), host2xhci(size, BIT_RANGE_INSERT(uint##size##_t, (hi), (lo), (value))), \ 115 115 XHCI_PIO_CHANGE_UDELAY); 116 117 /** HC capability registers: section 5.3 */ 118 typedef const struct xhci_cap_regs { 119 120 /* Size of this structure, offset for the operation registers */ 121 const ioport8_t caplength; 122 123 const PADD8; 124 125 /* BCD of specification version */ 126 const ioport16_t hciversion; 127 128 /* 129 * 7:0 - MaxSlots 130 * 18:8 - MaxIntrs 131 * 31:24 - MaxPorts 132 */ 133 const ioport32_t hcsparams1; 134 135 /* 136 * 0:3 - IST 137 * 7:4 - ERST Max 138 * 21:25 - Max Scratchpad Bufs Hi 139 * 26 - SPR 140 * 31:27 - Max Scratchpad Bufs Lo 141 */ 142 const ioport32_t hcsparams2; 143 144 /* 145 * 7:0 - U1 Device Exit Latency 146 * 31:16 - U2 Device Exit Latency 147 */ 148 const ioport32_t hcsparams3; 149 150 /* 151 * 11 10 9 8 7 6 5 4 3 2 1 0 152 * 11:0 - CFC SEC SPC PAE NSS LTC C PIND PPC CSZ BNC AC64 153 * 15:12 - MaxPSASize 154 * 31:16 - xECP 155 */ 156 const ioport32_t hccparams1; 157 158 /* 159 * 31:2 - Doorbell Array Offset 160 */ 161 const ioport32_t dboff; 162 163 /* 164 * 31:5 - Runtime Register Space Offset 165 */ 166 const ioport32_t rtsoff; 167 168 /* 169 * 5 4 3 2 1 0 170 * 5:0 - Flags: CIC LEC CTC FSC CMC U3C 171 */ 172 const ioport32_t hccparams2; 173 174 // the rest to operational registers is reserved 175 } xhci_cap_regs_t; 116 176 117 177 /* … … 154 214 #define XHCI_CAP_CIC hccparams2, 32, FLAG, 5 155 215 156 /** HC capability registers: section 5.3 */157 typedef const struct xhci_cap_regs {158 159 /* Size of this structure, offset for the operation registers */160 const ioport8_t caplength;161 162 const PADD8;163 164 /* BCD of specification version */165 const ioport16_t hciversion;166 167 /*168 * 7:0 - MaxSlots169 * 18:8 - MaxIntrs170 * 31:24 - MaxPorts171 */172 const ioport32_t hcsparams1;173 174 /*175 * 0:3 - IST176 * 7:4 - ERST Max177 * 21:25 - Max Scratchpad Bufs Hi178 * 26 - SPR179 * 31:27 - Max Scratchpad Bufs Lo180 */181 const ioport32_t hcsparams2;182 183 /*184 * 7:0 - U1 Device Exit Latency185 * 31:16 - U2 Device Exit Latency186 */187 const ioport32_t hcsparams3;188 189 /*190 * 11 10 9 8 7 6 5 4 3 2 1 0191 * 11:0 - CFC SEC SPC PAE NSS LTC C PIND PPC CSZ BNC AC64192 * 15:12 - MaxPSASize193 * 31:16 - xECP194 */195 const ioport32_t hccparams1;196 197 /*198 * 31:2 - Doorbell Array Offset199 */200 const ioport32_t dboff;201 202 /*203 * 31:5 - Runtime Register Space Offset204 */205 const ioport32_t rtsoff;206 207 /*208 * 5 4 3 2 1 0209 * 5:0 - Flags: CIC LEC CTC FSC CMC U3C210 */211 const ioport32_t hccparams2;212 213 // the rest to operational registers is reserved214 } xhci_cap_regs_t;215 216 217 216 /** 218 217 * XHCI Port Register Set: section 5.4, table 32 … … 240 239 * 16 - Force Link PM Accept 241 240 * USB2: 242 * 0:2- L1S241 * 2:0 - L1S 243 242 * 3 - RWE 244 243 * 7:4 - BESL … … 266 265 } xhci_port_regs_t; 267 266 267 #define XHCI_PORT_CCS portsc, 32, FLAG, 0 268 #define XHCI_PORT_PED portsc, 32, FLAG, 1 269 #define XHCI_PORT_OCA portsc, 32, FLAG, 3 270 #define XHCI_PORT_PR portsc, 32, FLAG, 4 271 #define XHCI_PORT_PLS portsc, 32, RANGE, 8, 5 272 #define XHCI_PORT_PP portsc, 32, FLAG, 9 273 #define XHCI_PORT_PIC portsc, 32, RANGE, 13, 10 274 #define XHCI_PORT_LWS portsc, 32, FLAG, 16 275 #define XHCI_PORT_CSC portsc, 32, FLAG, 17 276 #define XHCI_PORT_PEC portsc, 32, FLAG, 18 277 #define XHCI_PORT_WRC portsc, 32, FLAG, 19 278 #define XHCI_PORT_OCC portsc, 32, FLAG, 20 279 #define XHCI_PORT_PRC portsc, 32, FLAG, 21 280 #define XHCI_PORT_PLC portsc, 32, FLAG, 22 281 #define XHCI_PORT_CEC portsc, 32, FLAG, 23 282 #define XHCI_PORT_CAS portsc, 32, FLAG, 24 283 #define XHCI_PORT_WCE portsc, 32, FLAG, 25 284 #define XHCI_PORT_WDE portsc, 32, FLAG, 26 285 #define XHCI_PORT_WOE portsc, 32, FLAG, 27 286 #define XHCI_PORT_DR portsc, 32, FLAG, 28 287 #define XHCI_PORT_WPR portsc, 32, FLAG, 29 288 289 #define XHCI_PORT_USB3_U1TO portpmsc, 32, RANGE, 7, 0 290 #define XHCI_PORT_USB3_U2TO portpmsc, 32, RANGE, 15, 8 291 #define XHCI_PORT_USB3_FLPMA portpmsc, 32, FLAG, 16 292 #define XHCI_PORT_USB3_LEC portli, 32, RANGE, 15, 0 293 #define XHCI_PORT_USB3_RLC portli, 32, RANGE, 19, 16 294 #define XHCI_PORT_USB3_TLC portli, 32, RANGE, 23, 20 295 296 #define XHCI_PORT_USB2_L1S portpmsc, 32, RANGE, 2, 0 297 #define XHCI_PORT_USB2_RWE portpmsc, 32, FLAG, 3 298 #define XHCI_PORT_USB2_BESL portpmsc, 32, RANGE, 7, 4 299 #define XHCI_PORT_USB2_L1DS portpmsc, 32, RANGE, 15, 8 300 #define XHCI_PORT_USB2_HLE portpmsc, 32, FLAG, 16 301 #define XHCI_PORT_USB2_TM portpmsc, 32, RANGE, 31, 28 302 #define XHCI_PORT_USB2_HIRDM porthlmpc, 32, RANGE, 1, 0 303 #define XHCI_PORT_USB2_L1TO porthlmpc, 32, RANGE, 9, 2 304 #define XHCI_PORT_USB2_BESLD porthlmpc, 32, RANGE, 13, 10 305 268 306 /** 269 307 * XHCI Operational Registers: section 5.4 … … 272 310 273 311 /* 274 * 3 2 1 0275 * 3:0 - HSE INTE HCRST R/S312 * 3 2 1 0 313 * 3:0 - HSEE INTE HCRST R/S 276 314 * 277 315 * 11 10 9 8 7 … … 286 324 * 287 325 * 12 11 10 9 8 288 * 12:8 - CE CNR SRE RSS SSS326 * 12:8 - HCE CNR SRE RSS SSS 289 327 */ 290 328 ioport32_t usbsts; … … 329 367 } xhci_op_regs_t; 330 368 369 #define XHCI_OP_RS usbcmd, 32, FLAG, 0 370 #define XHCI_OP_HCRST usbcmd, 32, FLAG, 1 371 #define XHCI_OP_INTE usbcmd, 32, FLAG, 2 372 #define XHCI_OP_HSEE usbcmd, 32, FLAG, 3 373 #define XHCI_OP_LHCRST usbcmd, 32, FLAG, 7 374 #define XHCI_OP_CSS usbcmd, 32, FLAG, 8 375 #define XHCI_OP_CRS usbcmd, 32, FLAG, 9 376 #define XHCI_OP_EWE usbcmd, 32, FLAG, 10 377 #define XHCI_OP_EU3S usbcmd, 32, FLAG, 11 378 #define XHCI_OP_CME usbcmd, 32, FLAG, 13 379 #define XHCI_OP_HCH usbsts, 32, FLAG, 0 380 #define XHCI_OP_HSE usbsts, 32, FLAG, 2 381 #define XHCI_OP_EINT usbsts, 32, FLAG, 3 382 #define XHCI_OP_PCD usbsts, 32, FLAG, 4 383 #define XHCI_OP_SSS usbsts, 32, FLAG, 8 384 #define XHCI_OP_RSS usbsts, 32, FLAG, 9 385 #define XHCI_OP_SRE usbsts, 32, FLAG, 10 386 #define XHCI_OP_CNR usbsts, 32, FLAG, 11 387 #define XHCI_OP_HCE usbsts, 32, FLAG, 12 388 #define XHCI_OP_PAGESIZE pagesize, 32, FIELD 389 #define XHCI_OP_NOTIFICATION dnctrl, 32, RANGE, 15, 0 390 #define XHCI_OP_RCS crcr_lo, 32, FLAG, 0 391 #define XHCI_OP_CS crcr_lo, 32, FLAG, 1 392 #define XHCI_OP_CA crcr_lo, 32, FLAG, 2 393 #define XHCI_OP_CRR crcr_lo, 32, FLAG, 3 394 #define XHCI_OP_CRCR_LO crcr_lo, 32, RANGE, 31, 6 395 #define XHCI_OP_CRCR_HI crcr_lo, 32, FIELD 396 331 397 /** 332 398 * Interrupter Register Set: section 5.5.2 … … 361 427 } xhci_interrupter_regs_t; 362 428 429 #define XHCI_INTR_IP iman, 32, FLAG, 0 430 #define XHCI_INTR_IE iman, 32, FLAG, 1 431 #define XHCI_INTR_IMI imod, 32, RANGE, 15, 0 432 #define XHCI_INTR_IMC imod, 32, RANGE, 31, 16 433 #define XHCI_INTR_ERSTSZ erstsz, 32, FIELD 434 #define XHCI_INTR_ERSTBA_LO erstba_lo, 32, FIELD 435 #define XHCI_INTR_ERSTBA_HI erstba_hi, 32, FIELD 436 #define XHCI_INTR_ERDP_LO erdp_lo, 32, FIELD 437 #define XHCI_INTR_ERDP_HI erdp_hi, 32, FIELD 438 363 439 /** 364 440 * XHCI Runtime registers: section 5.5 … … 371 447 xhci_interrupter_regs_t ir[1024]; 372 448 } xhci_rt_regs_t; 449 450 #define XHCI_RT_MFINDEX mfindex, 32, FIELD 373 451 374 452 #endif
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