Ignore:
Timestamp:
2012-08-14T18:16:39Z (12 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
669f5cae
Parents:
76d92db1 (diff), 4802dd7 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/lib/c/arch/abs32le/_link.ld.in

    r76d92db1 rcddcc4a3  
    1414SECTIONS {
    1515#ifdef LOADER
     16        . = 0x70001000 + SIZEOF_HEADERS;
     17       
    1618        .interp : {
    1719                *(.interp);
    18         } :interp
    19        
    20         . = 0x70001000 + SIZEOF_HEADERS;
     20        } :interp :text
    2121#else
    2222        . = 0x1000 + SIZEOF_HEADERS;
    2323#endif
     24       
     25        /* Make sure the code is aligned reasonably */
     26        . = ALIGN(., 16);
     27       
    2428        .text : {
    2529                *(.text .text.*);
Note: See TracChangeset for help on using the changeset viewer.