Changeset c6a7b3a in mainline for kernel/arch/mips32/include/arch/mm/tlb.h

Timestamp:

2013-03-28T20:39:16Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2d1fdcad

Parents:

cc3c27ad (diff), 5d9fce4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

mainline changes

File:

• kernel/arch/mips32/include/arch/mm/tlb.h (modified) (2 diffs)

kernel/arch/mips32/include/arch/mm/tlb.h

@@ -41 +41 @@
 #include <trace.h>
 
+#if defined(PROCESSOR_R4000)
 #define TLB_ENTRY_COUNT  48
+#define TLB_INDEX_BITS   6
+#elif defined(PROCESSOR_4Kc)
+#define TLB_ENTRY_COUNT  16
+#define TLB_INDEX_BITS   4
+#else
+#error Please define TLB_ENTRY_COUNT for the target processor.
+#endif
 
-#define TLB_WIRED               1
-#define TLB_KSTACK_WIRED_INDEX  0
+#define TLB_WIRED               0 
 
 #define TLB_PAGE_MASK_4K    (0x000 << 13)
@@ -112 +119 @@
 #ifdef __BE__
                 unsigned p : 1;
-                unsigned : 25;
-                unsigned index : 6;
+                unsigned : 32 - TLB_INDEX_BITS - 1;
+                unsigned index : TLB_INDEX_BITS;
 #else
-                unsigned index : 6;
-                unsigned : 25;
+                unsigned index : TLB_INDEX_BITS;
+                unsigned : 32 - TLB_INDEX_BITS - 1;
                 unsigned p : 1;
 #endif