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Changeset c48de91 in mainline


Ignore:
Timestamp:
2019-06-09T11:51:56Z (20 months ago)
Author:
Jakub Jermar <jakub@…>
Branches:
master
Children:
0716a1f
Parents:
2a103b5
Message:

Hide macros used internally by the i8259 driver

Location:
kernel/genarch
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/include/genarch/drivers/i8259/i8259.h

    r2a103b5 rc48de91  
    4141#include <stdbool.h>
    4242
    43 /* ICW1 bits */
    44 #define PIC_ICW1           (1 << 4)
    45 #define PIC_ICW1_NEEDICW4  (1 << 0)
    46 
    47 /* OCW3 bits */
    48 #define PIC_OCW3           (1 << 3)
    49 #define PIC_OCW3_READ_ISR  (3 << 0)
    50 
    51 /* OCW4 bits */
    52 #define PIC_OCW4           (0 << 3)
    53 #define PIC_OCW4_NSEOI     (1 << 5)
    54 
    55 #define PIC0_IRQ_COUNT      8
    56 #define PIC1_IRQ_COUNT      8
    57 
    58 #define PIC0_IRQ_PIC1       2
    59 
    6043typedef struct {
    6144        ioport8_t port1;
  • kernel/genarch/src/drivers/i8259/i8259.c

    r2a103b5 rc48de91  
    3232/**
    3333 * @file
    34  * @brief PIC driver.
     34 * @brief i8259 driver.
    3535 *
    3636 * Programmable Interrupt Controller for UP systems based on i8259 chip.
     
    4242#include <log.h>
    4343#include <interrupt.h>
     44
     45/* ICW1 bits */
     46#define I8259_ICW1           (1 << 4)
     47#define I8259_ICW1_NEEDICW4  (1 << 0)
     48
     49/* OCW3 bits */
     50#define I8259_OCW3           (1 << 3)
     51#define I8259_OCW3_READ_ISR  (3 << 0)
     52
     53/* OCW4 bits */
     54#define I8259_OCW4           (0 << 3)
     55#define I8259_OCW4_NSEOI     (1 << 5)
     56
     57#define I8259_IRQ_COUNT 8
     58
     59#define I8259_IRQ_SLAVE 2
    4460
    4561static const char *i8259_get_name(void);
     
    6480
    6581        /* ICW1: this is ICW1, ICW4 to follow */
    66         pio_write_8(&pic0->port1, PIC_ICW1 | PIC_ICW1_NEEDICW4);
     82        pio_write_8(&pic0->port1, I8259_ICW1 | I8259_ICW1_NEEDICW4);
    6783
    6884        /* ICW2: IRQ 0 maps to interrupt vector address irq0_vec */
    6985        pio_write_8(&pic0->port2, irq0_vec);
    7086
    71         /* ICW3: pic1 using IRQ PIC0_IRQ_PIC1 */
    72         pio_write_8(&pic0->port2, 1 << PIC0_IRQ_PIC1);
     87        /* ICW3: pic1 using IRQ I8259_IRQ_SLAVE */
     88        pio_write_8(&pic0->port2, 1 << I8259_IRQ_SLAVE);
    7389
    7490        /* ICW4: i8086 mode */
     
    7692
    7793        /* ICW1: ICW1, ICW4 to follow */
    78         pio_write_8(&pic1->port1, PIC_ICW1 | PIC_ICW1_NEEDICW4);
     94        pio_write_8(&pic1->port1, I8259_ICW1 | I8259_ICW1_NEEDICW4);
    7995
    8096        /* ICW2: IRQ 8 maps to interrupt vector address irq0_vec + 8 */
    81         pio_write_8(&pic1->port2, irq0_vec + PIC0_IRQ_COUNT);
     97        pio_write_8(&pic1->port2, irq0_vec + I8259_IRQ_COUNT);
    8298
    83         /* ICW3: pic1 is known as PIC0_IRQ_PIC1 */
    84         pio_write_8(&pic1->port2, PIC0_IRQ_PIC1);
     99        /* ICW3: pic1 is known as I8259_IRQ_SLAVE */
     100        pio_write_8(&pic1->port2, I8259_IRQ_SLAVE);
    85101
    86102        /* ICW4: i8086 mode */
    87103        pio_write_8(&pic1->port2, 1);
    88104
    89         i8259_disable_irqs(0xffff);             /* disable all irq's */
    90         i8259_enable_irqs(1 << PIC0_IRQ_PIC1);  /* but enable PIC0_IRQ_PIC1 */
     105        /* disable all irq's */
     106        i8259_disable_irqs(0xffff);
     107        /* but enable I8259_IRQ_SLAVE */
     108        i8259_enable_irqs(1 << I8259_IRQ_SLAVE);
    91109}
    92110
     
    105123                    (uint8_t) (x & (~(irqmask & 0xff))));
    106124        }
    107         if (irqmask >> PIC0_IRQ_COUNT) {
     125        if (irqmask >> I8259_IRQ_COUNT) {
    108126                x = pio_read_8(&saved_pic1->port2);
    109127                pio_write_8(&saved_pic1->port2,
    110                     (uint8_t) (x & (~(irqmask >> PIC0_IRQ_COUNT))));
     128                    (uint8_t) (x & (~(irqmask >> I8259_IRQ_COUNT))));
    111129        }
    112130}
     
    121139                    (uint8_t) (x | (irqmask & 0xff)));
    122140        }
    123         if (irqmask >> PIC0_IRQ_COUNT) {
     141        if (irqmask >> I8259_IRQ_COUNT) {
    124142                x = pio_read_8(&saved_pic1->port2);
    125143                pio_write_8(&saved_pic1->port2,
    126                     (uint8_t) (x | (irqmask >> PIC0_IRQ_COUNT)));
     144                    (uint8_t) (x | (irqmask >> I8259_IRQ_COUNT)));
    127145        }
    128146}
     
    130148void i8259_eoi(unsigned int irq)
    131149{
    132         if (irq >= PIC0_IRQ_COUNT)
    133                 pio_write_8(&saved_pic1->port1, PIC_OCW4 | PIC_OCW4_NSEOI);
    134         pio_write_8(&saved_pic0->port1, PIC_OCW4 | PIC_OCW4_NSEOI);
     150        if (irq >= I8259_IRQ_COUNT)
     151                pio_write_8(&saved_pic1->port1, I8259_OCW4 | I8259_OCW4_NSEOI);
     152        pio_write_8(&saved_pic0->port1, I8259_OCW4 | I8259_OCW4_NSEOI);
    135153}
    136154
    137155bool i8259_is_spurious(unsigned int irq)
    138156{
    139         pio_write_8(&saved_pic0->port1, PIC_OCW3 | PIC_OCW3_READ_ISR);
    140         pio_write_8(&saved_pic1->port1, PIC_OCW3 | PIC_OCW3_READ_ISR);
     157        pio_write_8(&saved_pic0->port1, I8259_OCW3 | I8259_OCW3_READ_ISR);
     158        pio_write_8(&saved_pic1->port1, I8259_OCW3 | I8259_OCW3_READ_ISR);
    141159        uint8_t isr_lo = pio_read_8(&saved_pic0->port1);
    142160        uint8_t isr_hi = pio_read_8(&saved_pic1->port1);
    143         return !(((isr_hi << PIC0_IRQ_COUNT) | isr_lo) & (1 << irq));
     161        return !(((isr_hi << I8259_IRQ_COUNT) | isr_lo) & (1 << irq));
    144162}
    145163
     
    147165{
    148166        /* For spurious IRQs from pic1, we need to isssue an EOI to pic0 */
    149         if (irq >= PIC0_IRQ_COUNT)
    150                 pio_write_8(&saved_pic0->port1, PIC_OCW4 | PIC_OCW4_NSEOI);
     167        if (irq >= I8259_IRQ_COUNT)
     168                pio_write_8(&saved_pic0->port1, I8259_OCW4 | I8259_OCW4_NSEOI);
    151169}
    152170
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