Changeset c124dce3 in mainline

Timestamp:

2013-01-24T19:48:43Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0e63d34, b1011dae

Parents:

cfeb368

Message:

arm32: Typos and comments.

File:

• kernel/arch/arm32/include/barrier.h (modified) (1 diff)

kernel/arch/arm32/include/barrier.h

@@ -105 +105 @@
 /* Available on all supported arms,
  * invalidates entire ICache so the written value does not matter. */
-//TODO might be PL1 only on armv5 -
+//TODO might be PL1 only on armv5-
 #define smc_coherence(a) \
 do { \
-        DCCMVAU_write((uint32_t)(a));  /* Write changed memory */\
-        write_barrier();             /* Wait for completion */\
-        ICIALLU_write(0);            /* Flush ICache */\
-        inst_barrier();              /* Wait for Inst refetch */\
+        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
+        write_barrier();               /* Wait for completion */\
+        ICIALLU_write(0);              /* Flush ICache */\
+        inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
-/* @note: Cache type register is not awailable in uspace. We would need
+/* @note: Cache type register is not available in uspace. We would need
  * to export the cache line value, or use syscall for uspace smc_coherence */
 #define smc_coherence_block(a, l) \