Changeset bfc5c9dd in mainline for uspace/drv/bus/usb/ohci/ohci_regs.h


Ignore:
Timestamp:
2012-02-23T20:42:30Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
815b244a
Parents:
ffcc5776
Message:

ohci: Use more generic approach to access registers(and convert endian).

Make hc initialization work by design, not by accident. (Fixes random hang on startup).
Queues still disabled.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/usb/ohci/ohci_regs.h

    rffcc5776 rbfc5c9dd  
    4242#define ohci_reg2host(value) uint32_t_le2host(value)
    4343
     44#define OHCI_WR(reg, val) reg = host2uint32_t_le(val)
     45#define OHCI_RD(reg) uint32_t_le2host(reg)
     46#define OHCI_SET(reg, val) reg |= host2uint32_t_le(val)
     47#define OHCI_CLR(reg, val) reg &= host2uint32_t_le(val)
     48
     49
    4450#define LEGACY_REGS_OFFSET 0x100
    4551
    … …  
    4753typedef struct ohci_regs {
    4854        const ioport32_t revision;
    49 #define R_REVISION_(reg) (ohci_reg2host(reg) & 0x3f)
    50 #define R_LEGACY_FLAG   host2ohci_reg(0x80)
     55#define R_REVISION_MASK (0x3f)
     56#define R_LEGACY_FLAG   (0x80)
    5157
    5258        ioport32_t control;
    … …  
    5662#define C_CBSR_1_3  (0x2)
    5763#define C_CBSR_1_4  (0x3)
    58 #define C_CBSR_GET(reg) (ohci_reg2host(reg) & 0x3)
    59 #define C_CBSR_SET(reg, value) \
    60 do { \
    61     reg = (reg & host2ohci_reg(~0x3) | host2ohci_reg(value & 0x3)) \
    62 } while (0)
    63 
    64 #define C_PLE host2ohci_reg(1 << 2)   /* Periodic list enable */
    65 #define C_IE  host2ohci_reg(1 << 3)   /* Isochronous enable */
    66 #define C_CLE host2ohci_reg(1 << 4)   /* Control list enable */
    67 #define C_BLE host2ohci_reg(1 << 5)   /* Bulk list enable */
     64#define C_CBSR_MASK (0x3)
     65#define C_CBSR_SHIFT 0
     66
     67#define C_PLE (1 << 2)   /* Periodic list enable */
     68#define C_IE  (1 << 3)   /* Isochronous enable */
     69#define C_CLE (1 << 4)   /* Control list enable */
     70#define C_BLE (1 << 5)   /* Bulk list enable */
    6871
    6972/* Host controller functional state */
    … …  
    7275#define C_HCFS_OPERATIONAL (0x2)
    7376#define C_HCFS_SUSPEND     (0x3)
    74 #define C_HCFS_GET(reg) ((ohci_reg2host(reg) >> 6) & 0x3)
     77#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3)
    7578#define C_HCFS_SET(reg, value) \
    7679do { \
    77     reg = (reg & host2ohci_reg(~(0x3 << 6))) \
    78         | host2ohci_reg((value & 0x3) << 6); \
     80        uint32_t r = OHCI_RD(reg); \
     81        r &= ~(0x3 << 6); \
     82        r |= (value & 0x3) << 6; \
     83        OHCI_WR(reg, r); \
    7984} while (0)
    8085
    81 #define C_IR  host2ohci_reg(1 << 8)  /* Interrupt routing, make sure it's 0 */
    82 #define C_RWC host2ohci_reg(1 << 9)  /* Remote wakeup connected, host specific */
    83 #define C_RWE host2ohci_reg(1 << 10)  /* Remote wakeup enable */
     86#define C_IR  (1 << 8)  /* Interrupt routing, make sure it's 0 */
     87#define C_RWC (1 << 9)  /* Remote wakeup connected, host specific */
     88#define C_RWE (1 << 10)  /* Remote wakeup enable */
    8489
    8590        ioport32_t command_status;
    86 #define CS_HCR host2ohci_reg(1 << 0)   /* Host controller reset */
    87 #define CS_CLF host2ohci_reg(1 << 1)   /* Control list filled */
    88 #define CS_BLF host2ohci_reg(1 << 2)   /* Bulk list filled */
    89 #define CS_OCR host2ohci_reg(1 << 3)   /* Ownership change request */
     91#define CS_HCR (1 << 0)   /* Host controller reset */
     92#define CS_CLF (1 << 1)   /* Control list filled */
     93#define CS_BLF (1 << 2)   /* Bulk list filled */
     94#define CS_OCR (1 << 3)   /* Ownership change request */
    9095#if 0
    9196#define CS_SOC_MASK (0x3) /* Scheduling overrun count */
    … …  
    100105        ioport32_t interrupt_enable;
    101106        ioport32_t interrupt_disable;
    102 #define I_SO   host2ohci_reg(1 << 0)   /* Scheduling overrun */
    103 #define I_WDH  host2ohci_reg(1 << 1)   /* Done head write-back */
    104 #define I_SF   host2ohci_reg(1 << 2)   /* Start of frame */
    105 #define I_RD   host2ohci_reg(1 << 3)   /* Resume detect */
    106 #define I_UE   host2ohci_reg(1 << 4)   /* Unrecoverable error */
    107 #define I_FNO  host2ohci_reg(1 << 5)   /* Frame number overflow */
    108 #define I_RHSC host2ohci_reg(1 << 6)   /* Root hub status change */
    109 #define I_OC   host2ohci_reg(1 << 30)  /* Ownership change */
    110 #define I_MI   host2ohci_reg(1 << 31)  /* Master interrupt (any/all) */
     107#define I_SO   (1 << 0)   /* Scheduling overrun */
     108#define I_WDH  (1 << 1)   /* Done head write-back */
     109#define I_SF   (1 << 2)   /* Start of frame */
     110#define I_RD   (1 << 3)   /* Resume detect */
     111#define I_UE   (1 << 4)   /* Unrecoverable error */
     112#define I_FNO  (1 << 5)   /* Frame number overflow */
     113#define I_RHSC (1 << 6)   /* Root hub status change */
     114#define I_OC   (1 << 30)  /* Ownership change */
     115#define I_MI   (1 << 31)  /* Master interrupt (any/all) */
    111116
    112117        /** HCCA pointer (see hw_struct hcca.h) */
    … …  
    134139        /** Frame time and max packet size for all transfers */
    135140        ioport32_t fm_interval;
    136 #define FMI_FL_GET(reg) (ohci_reg2host(reg) & 0x3fff)
    137 #if 0   
    138141#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
    139142#define FMI_FI_SHIFT (0)
    … …  
    141144#define FMI_FSMPS_SHIFT (16)
    142145#define FMI_TOGGLE_FLAG (1 << 31)
    143 #endif
    144146
    145147        /** Bit times remaining in current frame */
    146148        const ioport32_t fm_remaining;
    147 #define FMR_R_GET(reg) (ohci_reg2host(reg) & 0x3fff)
    148 #if 0   
    149149#define FMR_FR_MASK FMI_FI_MASK
    150150#define FMR_FR_SHIFT FMI_FI_SHIFT
    151151#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
    152 #endif
     152
    153153        /** Frame number */
    154154        const ioport32_t fm_number;
    155 #if 0
    156155#define FMN_NUMBER_MASK (0xffff)
    157 #endif
     156
    158157        /** Remaining bit time in frame to start periodic transfers */
    159158        ioport32_t periodic_start;
    160 #define PS_GET(reg) (ohci_reg2host(reg) & 0x3fff)
    161 #define PS_SET(reg, value) \
    162 do { \
    163         reg = (reg & host2ohci_reg(~0x3fff)) | host2ohci_reg(value & 0x3fff); \
    164 } while (0)
     159#define PS_MASK 0x3fff
     160#define PS_SHIFT 0
    165161
    166162        /** Threshold for starting LS transaction */
    167163        ioport32_t ls_threshold;
    168 //#define LST_LST_MASK (0x7fff)
     164#define LST_LST_MASK (0x7fff)
    169165
    170166        /** The first root hub control register */
    171167        ioport32_t rh_desc_a;
    172168/** Number of downstream ports, max 15 */
    173 #define RHDA_NDS(reg) (ohci_reg2host(reg) & 0xff)
     169#define RHDA_NDS_MASK  (0xff)
    174170/** Power switching mode: 0-global, 1-per port*/
    175 #define RHDA_PSM_FLAG  host2ohci_reg(1 << 8)
     171#define RHDA_PSM_FLAG  (1 << 8)
    176172/** No power switch: 1-power on, 0-use PSM*/
    177 #define RHDA_NPS_FLAG  host2ohci_reg(1 << 9)
     173#define RHDA_NPS_FLAG  (1 << 9)
    178174/** 1-Compound device, must be 0 */
    179 #define RHDA_DT_FLAG   host2ohci_reg(1 << 10)
     175#define RHDA_DT_FLAG   (1 << 10)
    180176/** Over-current mode: 0-global, 1-per port */
    181 #define RHDA_OCPM_FLAG host2ohci_reg(1 << 11)
     177#define RHDA_OCPM_FLAG (1 << 11)
    182178/** OC control: 0-use OCPM, 1-OC off */
    183 #define RHDA_NOCP_FLAG host2ohci_reg(1 << 12)
     179#define RHDA_NOCP_FLAG (1 << 12)
    184180/** Power on to power good time */
    185 #define RHDA_POTPGT(reg) (ohci_reg2host(reg) >> 24)
     181#define RHDA_POTPGT_SHIFT   24
    186182
    187183        /** The other root hub control register */
    188184        ioport32_t rh_desc_b;
    189185/** Device removable mask */
    190 #define RHDB_DR_READ(reg) (ohci_reg2host(reg) & 0xffff)
    191 #define RHDB_DR_WRITE(val) host2ohci_reg(val & 0xffff)
     186#define RHDB_DR_SHIFT   0
     187#define RHDB_DR_MASK    0xffff
    192188/** Power control mask */
    193 #define RHDB_PCC_READ(reg) (ohci_reg2host(reg) >> 16)
    194 #define RHDB_PCC_WRITE(val) host2ohci_reg(val << 16)
    195 /* Port device removable status */
    196 #define RHDB_DR_FLAG(port) \
    197     host2ohci_reg(((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
    198 /* Port power control status: 1-per port power control, 0-global power switch */
    199 #define RHDB_PPC_FLAG(port) \
    200     host2ohci_reg(((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
     189#define RHDB_PCC_MASK (0xffff)
     190#define RHDB_PCC_SHIFT 16
    201191
    202192        /** Root hub status register */
    … …  
    207197 *        specified in PPCM(RHDB), or all ports,
    208198 *        if power is set globally */
    209 #define RHS_LPS_FLAG  host2ohci_reg(1 <<  0)
     199#define RHS_LPS_FLAG  (1 <<  0)
    210200#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
    211201/** Over-current indicator, if per-port: 0 */
    212 #define RHS_OCI_FLAG  host2ohci_reg(1 <<  1)
     202#define RHS_OCI_FLAG  (1 <<  1)
    213203
    214204/* read: 0-connect status change does not wake HC
    215205 *       1-connect status change wakes HC
    216206 * write: 1-set DRWE, 0-no effect */
    217 #define RHS_DRWE_FLAG host2ohci_reg(1 << 15)
     207#define RHS_DRWE_FLAG (1 << 15)
    218208#define RHS_SET_DRWE RHS_DRWE_FLAG
    219209/* read: 0,
    … …  
    222212 *        specified in PPCM(RHDB), or all ports,
    223213 *        if power is set globally */
    224 #define RHS_LPSC_FLAG host2ohci_reg(1 << 16)
     214#define RHS_LPSC_FLAG (1 << 16)
    225215#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
    226216/** Over-current change indicator*/
    227 #define RHS_OCIC_FLAG host2ohci_reg(1 << 17)
    228 #define RHS_CLEAR_DRWE host2ohci_reg(1 << 31)
     217#define RHS_OCIC_FLAG (1 << 17)
     218#define RHS_CLEAR_DRWE (1 << 31)
    229219
    230220        /** Root hub per port status */
    231221        ioport32_t rh_port_status[];
    232 #define RHPS_CCS_FLAG host2ohci_reg(1 << 0) /* r: current connect status,
     222#define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
    233223                                               * w: 1-clear port enable, 0-N/S*/
    234224#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
    235 #define RHPS_PES_FLAG host2ohci_reg(1 << 1) /* r: port enable status
     225#define RHPS_PES_FLAG (1 << 1) /* r: port enable status
    236226                                              * w: 1-set port enable, 0-N/S */
    237227#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
    238 #define RHPS_PSS_FLAG host2ohci_reg(1 << 2) /* r: port suspend status
     228#define RHPS_PSS_FLAG (1 << 2) /* r: port suspend status
    239229                                               * w: 1-set port suspend, 0-N/S */
    240230#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
    241 #define RHPS_POCI_FLAG host2ohci_reg(1 << 3) /* r: port over-current
     231#define RHPS_POCI_FLAG (1 << 3) /* r: port over-current
    242232                                                * (if reports are per-port
    243233                                                * w: 1-clear port suspend
    … …  
    245235                                                *    0-nothing */
    246236#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
    247 #define RHPS_PRS_FLAG host2ohci_reg(1 << 4) /* r: port reset status
     237#define RHPS_PRS_FLAG (1 << 4) /* r: port reset status
    248238                                               * w: 1-set port reset, 0-N/S */
    249239#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
    250 #define RHPS_PPS_FLAG host2ohci_reg(1 << 8) /* r: port power status
     240#define RHPS_PPS_FLAG (1 << 8) /* r: port power status
    251241                                              * w: 1-set port power, 0-N/S */
    252242#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
    253 #define RHPS_LSDA_FLAG host2ohci_reg(1 << 9) /* r: low speed device attached
     243#define RHPS_LSDA_FLAG (1 << 9) /* r: low speed device attached
    254244                                                * w: 1-clear port power, 0-N/S*/
    255245#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
    256 #define RHPS_CSC_FLAG  host2ohci_reg(1 << 16) /* connect status change WC */
    257 #define RHPS_PESC_FLAG host2ohci_reg(1 << 17) /* port enable status change WC */
    258 #define RHPS_PSSC_FLAG host2ohci_reg(1 << 18) /* port suspend status change WC */
    259 #define RHPS_OCIC_FLAG host2ohci_reg(1 << 19) /* port over-current change WC */
    260 #define RHPS_PRSC_FLAG host2ohci_reg(1 << 20) /* port reset status change WC */
    261 #define RHPS_CHANGE_WC_MASK host2ohci_reg(0x1f0000)
    262 /** OHCI designers were kind enough to make bits correspond to feature # */
    263 #define RHPS_FEATURE_BIT(feature) host2ohci_reg(1 << feature)
     246#define RHPS_CSC_FLAG  (1 << 16) /* connect status change WC */
     247#define RHPS_PESC_FLAG (1 << 17) /* port enable status change WC */
     248#define RHPS_PSSC_FLAG (1 << 18) /* port suspend status change WC */
     249#define RHPS_OCIC_FLAG (1 << 19) /* port over-current change WC */
     250#define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
     251#define RHPS_CHANGE_WC_MASK (0x1f0000)
    264252} __attribute__((packed)) ohci_regs_t;
    265253#endif
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