Changeset bfb6576 in mainline for boot/arch/arm32/src/asm.S

Timestamp:

2013-01-23T00:12:15Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b80d132

Parents:

c19808fd

Message:

arm32, boot: Rework boot time cache handling. Enable Icache early.

Dcache still hangs after jumping to kernel.

File:

• boot/arch/arm32/src/asm.S (modified) (2 diffs)

boot/arch/arm32/src/asm.S

@@ -66 +66 @@
         # r2 is a kernel text end
 
-        # make sure kernel is flushed and available in memory
-        # Disable I-cache and D-cache before the kernel is started.
-        # TODO disabling DCache should not be necessary...
-#define CP15_C1_IC              12
-#define CP15_C1_DC              2
-        mrc     p15, 0, r4, c1, c0, 0
-        bic     r4, r4, #(1 << CP15_C1_DC)
-        bic     r4, r4, #(1 << CP15_C1_IC)
-        mcr     p15, 0, r4, c1, c0, 0
-
-        # use r4 as a moving pointer
-        mov r4, r0
-3:
-        # DCCMVAC (flush by virt address, to the point of coherence)
-        mcr p15, 0, r4, c7, c10, 1
-        # TODO: it would be better to use cacheline size
-        add r4, r4, #4
-        # are we there yet?
-        cmp r4, r2
-        blt 3b
-        nop
-        mov r4, #0
         
         #Wait for the operations to complete
@@ -99 +77 @@
         # Clean ICache and BPredictors, r4 ignored (SBZ)
         mcr p15, 0, r4, c7, c5, 0
+        nop
 
         #Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         isb
+        nop
 #else
         # cp15 isb
         mcr p15, 0, r4, c7, c5, 4
+        nop
 #endif