Changeset bd48f4c in mainline for kernel/arch/sparc64/include/sun4v/cpu.h

Timestamp:

2010-07-12T10:53:30Z (14 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bd11d3e

Parents:

c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/sparc64/include/sun4v/cpu.h (modified) (2 diffs)

kernel/arch/sparc64/include/sun4v/cpu.h

@@ -37 +37 @@
 
 /** Maximum number of virtual processors. */
-#define MAX_NUM_STRANDS         64
+#define MAX_NUM_STRANDS  64
 
 /** Maximum number of logical processors in a processor core */
-#define MAX_CORE_STRANDS        8
+#define MAX_CORE_STRANDS  8
 
 #ifndef __ASM__
@@ -59 +59 @@
 
 typedef struct cpu_arch {
-        uint64_t id;                    /**< virtual processor ID */
-        uint32_t clock_frequency;       /**< Processor frequency in Hz. */
-        uint64_t next_tick_cmpr;        /**< Next clock interrupt should be
-                                             generated when the TICK register
-                                             matches this value. */
-        exec_unit_t *exec_unit;         /**< Physical core. */
-        unsigned long proposed_nrdy;    /**< Proposed No. of ready threads
-                                             so that cores are equally balanced. */
+        uint64_t id;                  /**< virtual processor ID */
+        uint32_t clock_frequency;     /**< Processor frequency in Hz. */
+        uint64_t next_tick_cmpr;      /**< Next clock interrupt should be
+                                           generated when the TICK register
+                                           matches this value. */
+        exec_unit_t *exec_unit;       /**< Physical core. */
+        unsigned long proposed_nrdy;  /**< Proposed No. of ready threads
+                                           so that cores are equally balanced. */
 } cpu_arch_t;
-
-#endif  
-
-#ifdef __ASM__
 
 #endif