Changeset bd48f4c in mainline for kernel/arch/sparc64/include/sun4u/cpu.h

Timestamp:

2010-07-12T10:53:30Z (14 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bd11d3e

Parents:

c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/sparc64/include/sun4u/cpu.h (modified) (4 diffs)

kernel/arch/sparc64/include/sun4u/cpu.h

@@ -36 +36 @@
 #define KERN_sparc64_sun4u_CPU_H_
 
-#define MANUF_FUJITSU           0x04
-#define MANUF_ULTRASPARC        0x17    /**< UltraSPARC I, UltraSPARC II */
-#define MANUF_SUN               0x3e
+#define MANUF_FUJITSU     0x04
+#define MANUF_ULTRASPARC  0x17  /**< UltraSPARC I, UltraSPARC II */
+#define MANUF_SUN         0x3e
 
-#define IMPL_ULTRASPARCI        0x10
-#define IMPL_ULTRASPARCII       0x11
-#define IMPL_ULTRASPARCII_I     0x12
-#define IMPL_ULTRASPARCII_E     0x13
-#define IMPL_ULTRASPARCIII      0x14
-#define IMPL_ULTRASPARCIII_PLUS 0x15
-#define IMPL_ULTRASPARCIII_I    0x16
-#define IMPL_ULTRASPARCIV       0x18
-#define IMPL_ULTRASPARCIV_PLUS  0x19
+#define IMPL_ULTRASPARCI         0x10
+#define IMPL_ULTRASPARCII        0x11
+#define IMPL_ULTRASPARCII_I      0x12
+#define IMPL_ULTRASPARCII_E      0x13
+#define IMPL_ULTRASPARCIII       0x14
+#define IMPL_ULTRASPARCIII_PLUS  0x15
+#define IMPL_ULTRASPARCIII_I     0x16
+#define IMPL_ULTRASPARCIV        0x18
+#define IMPL_ULTRASPARCIV_PLUS   0x19
 
-#define IMPL_SPARC64V           0x5
+#define IMPL_SPARC64V  0x5
 
 #ifndef __ASM__
@@ -58 +58 @@
 #include <arch/regdef.h>
 #include <arch/asm.h>
+#include <trace.h>
 
 #ifdef CONFIG_SMP
@@ -64 +65 @@
 
 typedef struct {
-        uint32_t mid;                   /**< Processor ID as read from
-                                             UPA_CONFIG/FIREPLANE_CONFIG. */
+        uint32_t mid;              /**< Processor ID as read from
+                                        UPA_CONFIG/FIREPLANE_CONFIG. */
         ver_reg_t ver;
-        uint32_t clock_frequency;       /**< Processor frequency in Hz. */
-        uint64_t next_tick_cmpr;        /**< Next clock interrupt should be
-                                             generated when the TICK register
-                                             matches this value. */
+        uint32_t clock_frequency;  /**< Processor frequency in Hz. */
+        uint64_t next_tick_cmpr;   /**< Next clock interrupt should be
+                                        generated when the TICK register
+                                        matches this value. */
 } cpu_arch_t;
 
-
-/**
- * Reads the module ID (agent ID/CPUID) of the current CPU.
+/** Read the module ID (agent ID/CPUID) of the current CPU.
+ *
  */
-static inline uint32_t read_mid(void)
+NO_TRACE static inline uint32_t read_mid(void)
 {
         uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
         icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
+        
 #if defined (US)
         return icbus_config & 0x1f;
@@ -91 +92 @@
 }
 
-#endif  
+#endif
 
 #endif