Changeset bd48f4c in mainline for kernel/arch/sparc64/include/barrier.h

Timestamp:

2010-07-12T10:53:30Z (14 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bd11d3e

Parents:

c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/sparc64/include/barrier.h (modified) (4 diffs)

kernel/arch/sparc64/include/barrier.h

@@ -27 +27 @@
  */
 
-/** @addtogroup sparc64 
+/** @addtogroup sparc64
  * @{
  */
@@ -36 +36 @@
 #define KERN_sparc64_BARRIER_H_
 
+#include <trace.h>
+
 #ifdef KERNEL
+
 #include <typedefs.h>
+
 #else
+
 #include <stdint.h>
+
 #endif
 
@@ -45 +51 @@
  * Our critical section barriers are prepared for the weakest RMO memory model.
  */
-#define CS_ENTER_BARRIER()                              \
-        asm volatile (                                  \
-                "membar #LoadLoad | #LoadStore\n"       \
-                ::: "memory"                            \
-        )
-#define CS_LEAVE_BARRIER()                              \
-        asm volatile (                                  \
-                "membar #StoreStore\n"                  \
-                "membar #LoadStore\n"                   \
-                ::: "memory"                            \
+#define CS_ENTER_BARRIER() \
+        asm volatile ( \
+                "membar #LoadLoad | #LoadStore\n" \
+                ::: "memory" \
         )
 
-#define memory_barrier()        \
-        asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
-#define read_barrier()          \
-        asm volatile ("membar #LoadLoad\n" ::: "memory")
-#define write_barrier()         \
-        asm volatile ("membar #StoreStore\n" ::: "memory")
+#define CS_LEAVE_BARRIER() \
+        asm volatile ( \
+                "membar #StoreStore\n" \
+                "membar #LoadStore\n" \
+                ::: "memory" \
+        )
 
-#define flush(a)                \
-        asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
+#define memory_barrier() \
+        asm volatile ( \
+                "membar #LoadLoad | #StoreStore\n" \
+                ::: "memory" \
+        )
+
+#define read_barrier() \
+        asm volatile ( \
+                "membar #LoadLoad\n" \
+                ::: "memory" \
+        )
+
+#define write_barrier() \
+        asm volatile ( \
+                "membar #StoreStore\n" \
+                ::: "memory" \
+        )
+
+#define flush(a) \
+        asm volatile ( \
+                "flush %[reg]\n" \
+                :: [reg] "r" ((a)) \
+                : "memory" \
+        )
 
 /** Flush Instruction pipeline. */
-static inline void flush_pipeline(void)
+NO_TRACE static inline void flush_pipeline(void)
 {
         uint64_t pc;
-
+        
         /*
          * The FLUSH instruction takes address parameter.
@@ -80 +102 @@
          * the %pc register will always be in the range mapped by
          * DTLB.
+         *
          */
-         
-        asm volatile (
-                "rd %%pc, %0\n"
-                "flush %0\n"
-                : "=&r" (pc)
+        
+        asm volatile (
+                "rd %%pc, %[pc]\n"
+                "flush %[pc]\n"
+                : [pc] "=&r" (pc)
         );
 }
 
 /** Memory Barrier instruction. */
-static inline void membar(void)
+NO_TRACE static inline void membar(void)
 {
-        asm volatile ("membar #Sync\n");
+        asm volatile (
+                "membar #Sync\n"
+        );
 }
 
 #if defined (US)
 
-#define smc_coherence(a)        \
-{                               \
-        write_barrier();        \
-        flush((a));             \
-}
+#define FLUSH_INVAL_MIN  4
 
-#define FLUSH_INVAL_MIN         4
-#define smc_coherence_block(a, l)                       \
-{                                                       \
-        unsigned long i;                                \
-        write_barrier();                                \
-        for (i = 0; i < (l); i += FLUSH_INVAL_MIN)      \
-                flush((void *)(a) + i);                 \
-}
+#define smc_coherence(a) \
+        do { \
+                write_barrier(); \
+                flush((a)); \
+        } while (0)
+
+#define smc_coherence_block(a, l) \
+        do { \
+                unsigned long i; \
+                write_barrier(); \
+                \
+                for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
+                        flush((void *)(a) + i); \
+        } while (0)
 
 #elif defined (US3)
 
-#define smc_coherence(a)        \
-{                               \
-        write_barrier();        \
-        flush_pipeline();       \
-}
+#define smc_coherence(a) \
+        do { \
+                write_barrier(); \
+                flush_pipeline(); \
+        } while (0)
 
-#define smc_coherence_block(a, l)       \
-{                                       \
-        write_barrier();                \
-        flush_pipeline();               \
-}
+#define smc_coherence_block(a, l) \
+        do { \
+                write_barrier(); \
+                flush_pipeline(); \
+        } while (0)
 
-#endif  /* defined(US3) */
+#endif  /* defined(US3) */
 
 #endif