Changeset bd48f4c in mainline for kernel/arch/abs32le/include/asm.h

Timestamp:

2010-07-12T10:53:30Z (14 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bd11d3e

Parents:

c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/abs32le/include/asm.h (modified) (8 diffs)

kernel/arch/abs32le/include/asm.h

@@ -38 +38 @@
 #include <typedefs.h>
 #include <config.h>
-
-static inline void asm_delay_loop(uint32_t usec)
-{
-}
-
-static inline __attribute__((noreturn)) void cpu_halt(void)
+#include <trace.h>
+
+NO_TRACE static inline void asm_delay_loop(uint32_t usec)
+{
+}
+
+NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
 {
         /* On real hardware this should stop processing further
@@ -53 +54 @@
 }
 
-static inline void cpu_sleep(void)
+NO_TRACE static inline void cpu_sleep(void)
 {
         /* On real hardware this should put the CPU into low-power
@@ -61 +62 @@
 }
 
-static inline void pio_write_8(ioport8_t *port, uint8_t val)
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
 }
@@ -73 +74 @@
  *
  */
-static inline void pio_write_16(ioport16_t *port, uint16_t val)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
 }
@@ -85 +86 @@
  *
  */
-static inline void pio_write_32(ioport32_t *port, uint32_t val)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
 }
@@ -97 +98 @@
  *
  */
-static inline uint8_t pio_read_8(ioport8_t *port)
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
         return 0;
@@ -110 +111 @@
  *
  */
-static inline uint16_t pio_read_16(ioport16_t *port)
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
         return 0;
@@ -123 +124 @@
  *
  */
-static inline uint32_t pio_read_32(ioport32_t *port)
-{
-        return 0;
-}
-
-static inline ipl_t interrupts_enable(void)
-{
-        /* On real hardware this unconditionally enables preemption
-           by internal and external interrupts.
-           
-           The return value stores the previous interrupt level. */
-        
-        return 0;
-}
-
-static inline ipl_t interrupts_disable(void)
-{
-        /* On real hardware this disables preemption by the usual
-           set of internal and external interrupts. This does not
-           apply to special non-maskable interrupts and sychronous
-           CPU exceptions.
-           
-           The return value stores the previous interrupt level. */
-        
-        return 0;
-}
-
-static inline void interrupts_restore(ipl_t ipl)
-{
-        /* On real hardware this either enables or disables preemption
-           according to the interrupt level value from the argument. */
-}
-
-static inline ipl_t interrupts_read(void)
-{
-        /* On real hardware the return value stores the current interrupt
-           level. */
-        
-        return 0;
-}
-
-static inline bool interrupts_disabled(void)
-{
-        /* On real hardware the return value is true iff interrupts are
-           disabled. */
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+{
+        return 0;
+}
+
+NO_TRACE static inline ipl_t interrupts_enable(void)
+{
+        /*
+         * On real hardware this unconditionally enables preemption
+         * by internal and external interrupts.
+         *
+         * The return value stores the previous interrupt level.
+         */
+        
+        return 0;
+}
+
+NO_TRACE static inline ipl_t interrupts_disable(void)
+{
+        /*
+         * On real hardware this disables preemption by the usual
+         * set of internal and external interrupts. This does not
+         * apply to special non-maskable interrupts and sychronous
+         * CPU exceptions.
+         *
+         * The return value stores the previous interrupt level.
+         */
+        
+        return 0;
+}
+
+NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+{
+        /*
+         * On real hardware this either enables or disables preemption
+         * according to the interrupt level value from the argument.
+         */
+}
+
+NO_TRACE static inline ipl_t interrupts_read(void)
+{
+        /*
+         * On real hardware the return value stores the current interrupt
+         * level.
+         */
+        
+        return 0;
+}
+
+NO_TRACE static inline bool interrupts_disabled(void)
+{
+        /*
+         * On real hardware the return value is true iff interrupts are
+         * disabled.
+         */
+        
         return false;
 }
 
-static inline uintptr_t get_stack_base(void)
-{
-        /* On real hardware this returns the address of the bottom
-           of the current CPU stack. The the_t structure is stored
-           on the bottom of stack and this is used to identify the
-           current CPU, current task, current thread and current
-           address space. */
+NO_TRACE static inline uintptr_t get_stack_base(void)
+{
+        /*
+         * On real hardware this returns the address of the bottom
+         * of the current CPU stack. The the_t structure is stored
+         * on the bottom of stack and this is used to identify the
+         * current CPU, current task, current thread and current
+         * address space.
+         */
         
         return 0;