Changeset b8e72fd1 in mainline for uspace/drv/bus/pci/pciintel/pci_regs.h

Timestamp:

2013-05-30T17:13:02Z (11 years ago)

Author:

Vojtech Horky <vojtechhorky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

98abd40

Parents:

be2bb4f (diff), 94dfb92 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

File:

• uspace/drv/bus/pci/pciintel/pci_regs.h (modified) (1 diff)

uspace/drv/bus/pci/pciintel/pci_regs.h

@@ -95 +95 @@
 #define PCI_BRIDGE_CTL                  0x3E
 
+/* PCI command flags */
+#define PCI_COMMAND_IO            0x001
+#define PCI_COMMAND_MEMORY        0x002
+#define PCI_COMMAND_MASTER        0x004
+#define PCI_COMMAND_SPECIAL       0x008
+#define PCI_COMMAND_INVALIDATE    0x010
+#define PCI_COMMAND_VGA_PALETTE   0x020
+#define PCI_COMMAND_PARITY        0x040
+#define PCI_COMMAND_WAIT          0x080
+#define PCI_COMMAND_SERR          0x100
+#define PCI_COMMAND_FAST_BACK     0x200
+#define PCI_COMMAND_INTX_DISABLE  0x400
+
 #endif