Changeset b17518e in mainline for kernel/arch/ia32/include/atomic.h
- Timestamp:
- 2012-08-05T01:18:21Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bc216a0
- Parents:
- f1c7755
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia32/include/atomic.h
rf1c7755 rb17518e 144 144 145 145 146 #define _atomic_cas_ ptr_impl(pptr, exp_val, new_val, old_val, prefix) \146 #define _atomic_cas_impl(pptr, exp_val, new_val, old_val, prefix) \ 147 147 asm volatile ( \ 148 148 prefix " cmpxchgl %[newval], %[ptr]\n" \ … … 165 165 { 166 166 void *old_val; 167 _atomic_cas_ ptr_impl(pptr, exp_val, new_val, old_val, "lock\n");167 _atomic_cas_impl(pptr, exp_val, new_val, old_val, "lock\n"); 168 168 return old_val; 169 169 } … … 177 177 { 178 178 void *old_val; 179 _atomic_cas_ ptr_impl(pptr, exp_val, new_val, old_val, "");179 _atomic_cas_impl(pptr, exp_val, new_val, old_val, ""); 180 180 return old_val; 181 181 } 182 182 183 183 184 /** Atomicaly sets *ptr to new_val and returns the previous value. */ 185 NO_TRACE static inline void * atomic_swap_ptr(void **pptr, void *new_val) 186 { 187 void *new_in_old_out = new_val; 188 189 asm volatile ( 190 "xchgl %[val], %[pptr]\n" 191 : [val] "+r" (new_in_old_out), 192 [pptr] "+m" (*pptr) 193 ); 194 195 return new_in_old_out; 184 #define _atomic_swap_impl(pptr, new_val) \ 185 ({ \ 186 typeof(*(pptr)) new_in_old_out = new_val; \ 187 asm volatile ( \ 188 "xchgl %[val], %[p_ptr]\n" \ 189 : [val] "+r" (new_in_old_out), \ 190 [p_ptr] "+m" (*pptr) \ 191 ); \ 192 \ 193 new_in_old_out; \ 194 }) 195 196 /* 197 * Issuing a xchg instruction always implies lock prefix semantics. 198 * Therefore, it is cheaper to use a cmpxchg without a lock prefix 199 * in a loop. 200 */ 201 #define _atomic_swap_local_impl(pptr, new_val) \ 202 ({ \ 203 typeof(*(pptr)) exp_val; \ 204 typeof(*(pptr)) old_val; \ 205 \ 206 do { \ 207 exp_val = *pptr; \ 208 _atomic_cas_impl(pptr, exp_val, new_val, old_val, ""); \ 209 } while (old_val != exp_val); \ 210 \ 211 old_val; \ 212 }) 213 214 215 /** Atomicaly sets *ptr to val and returns the previous value. */ 216 NO_TRACE static inline void * atomic_set_return_ptr(void **pptr, void *val) 217 { 218 return _atomic_swap_impl(pptr, val); 196 219 } 197 220 … … 201 224 * NOT atomic wrt to other cpus. 202 225 */ 203 NO_TRACE static inline void * atomic_swap_ptr_local(void **pptr, void *new_val) 204 { 205 /* 206 * Issuing a xchg instruction always implies lock prefix semantics. 207 * Therefore, it is cheaper to use a cmpxchg without a lock prefix 208 * in a loop. 209 */ 210 void *exp_val; 211 void *old_val; 212 213 do { 214 exp_val = *pptr; 215 old_val = atomic_cas_ptr_local(pptr, exp_val, new_val); 216 } while (old_val != exp_val); 217 218 return old_val; 219 } 226 NO_TRACE static inline void * atomic_set_return_ptr_local( 227 void **pptr, void *new_val) 228 { 229 return _atomic_swap_local_impl(pptr, new_val); 230 } 231 232 /** Atomicaly sets *ptr to val and returns the previous value. */ 233 NO_TRACE static inline native_t atomic_set_return_native_t( 234 native_t *p, native_t val) 235 { 236 return _atomic_swap_impl(p, val); 237 } 238 239 /** Sets *ptr to new_val and returns the previous value. NOT smp safe. 240 * 241 * This function is only atomic wrt to local interrupts and it is 242 * NOT atomic wrt to other cpus. 243 */ 244 NO_TRACE static inline native_t atomic_set_return_native_t_local( 245 native_t *p, native_t new_val) 246 { 247 return _atomic_swap_local_impl(p, new_val); 248 } 249 220 250 221 251 #undef _atomic_cas_ptr_impl 252 #undef _atomic_swap_impl 253 #undef _atomic_swap_local_impl 222 254 223 255 #endif
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