Changeset afe5e09 in mainline

Timestamp:

2015-10-06T20:20:50Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

15fbe6a

Parents:

d5610b9

Message:

Define CP15_C7_MVA_ALIGN for all supported ARM processors.

• Use CP15_C7_MVA_ALIGN in smc_coherence() and smc_coherence_block().

Location:

kernel/arch/arm32/include/arch

Files:

• barrier.h (modified) (3 diffs)
• cp15.h (modified) (1 diff)

kernel/arch/arm32/include/arch/barrier.h

@@ -40 +40 @@
 #include <arch/cache.h>
 #include <arch/cp15.h>
+#include <align.h>
 #else
 #include <libarch/cp15.h>
@@ -115 +116 @@
 #define smc_coherence(a) \
 do { \
-        dcache_clean_mva_pou((uintptr_t) a);\
+        dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
         write_barrier();               /* Wait for completion */\
         icache_invalidate();\
@@ -124 +125 @@
 #define smc_coherence_block(a, l) \
 do { \
-        for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
+        for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
+            addr += CP15_C7_MVA_ALIGN) \
                 smc_coherence(addr); \
 } while (0)

kernel/arch/arm32/include/arch/cp15.h

@@ -395 +395 @@
  */
 
+#if defined(PROCESSOR_cortex_a8)
+#define CP15_C7_MVA_ALIGN       64
+#elif defined(PROCESSOR_arm1176)
+#define CP15_C7_MVA_ALIGN       32
+#elif defined(PROCESSOR_arm926ej_s)
+#define CP15_C7_MVA_ALIGN       32
+#elif defined(PROCESSOR_arm920t)
+#define CP15_C7_MVA_ALIGN       32
+#else
+#error Unknow MVA alignment
+#endif
+
 #if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);