Changeset ae8d7b0 in mainline for boot/arch/riscv64/src/ucb.c

Timestamp:

2017-08-21T18:23:39Z (7 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c58441d

Parents:

fdc29300

Message:

riscv64: update to the latest Privileged Architecture specification (1.10)

File:

• boot/arch/riscv64/src/ucb.c (modified) (2 diffs)

boot/arch/riscv64/src/ucb.c

@@ -31 +31 @@
 #include <macros.h>
 
+volatile uint64_t tohost __attribute__((section(".htif")));
+volatile uint64_t fromhost __attribute__((section(".htif")));
+
+static void poll_fromhost()
+{
+        uint64_t val = fromhost;
+        if (!val)
+                return;
+        
+        fromhost = 0;
+}
+
 void htif_cmd(uint8_t device, uint8_t cmd, uint64_t payload)
 {
@@ -36 +48 @@
             (((uint64_t) cmd) << 48) |
             (payload & UINT64_C(0xffffffffffff));
-        uint64_t retval;
         
-        do {
-                asm volatile (
-                        "csrrw %[retval], " STRING(CSR_MTOHOST) ", %[val]\n"
-                        : [retval] "=r" (retval)
-                        : [val] "r" (val)
-                );
-        } while (retval != 0);
+        while (tohost)
+                poll_fromhost();
+        
+        tohost = val;
 }