Changeset add04f7 in mainline for kernel/arch/ia32/include/asm.h

Timestamp:

2009-03-03T15:20:49Z (15 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f24d300

Parents:

deca67b

Message:

better inline assembler readability using the new symbolic syntax

File:

• kernel/arch/ia32/include/asm.h (modified) (26 diffs)

kernel/arch/ia32/include/asm.h

@@ -28 +28 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -57 +57 @@
  *
  * Halt the current CPU until interrupt event.
+ *
  */
 static inline void cpu_halt(void)
@@ -69 +70 @@
 
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
-    { \
-        unative_t res; \
-        asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
-        return res; \
-    }
+        { \
+                unative_t res; \
+                asm volatile ( \
+                        "movl %%" #reg ", %[res]" \
+                        : [res] "=r" (res) \
+                ); \
+                return res; \
+        }
 
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
-    { \
-        asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
-    }
+        { \
+                asm volatile ( \
+                        "movl %[regn], %%" #reg \
+                        :: [regn] "r" (regn) \
+                ); \
+        }
 
 GEN_READ_REG(cr0)
@@ -105 +112 @@
  * @param port Port to write to
  * @param val Value to write
+ *
  */
 static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
-        asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port));
+        asm volatile (
+                "outb %b[val], %w[port]\n"
+                :: [val] "a" (val), [port] "d" (port)
+        );
 }
 
@@ -117 +128 @@
  * @param port Port to write to
  * @param val Value to write
+ *
  */
 static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
-        asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port));
+        asm volatile (
+                "outw %w[val], %w[port]\n"
+                :: [val] "a" (val), [port] "d" (port)
+        );
 }
 
@@ -129 +144 @@
  * @param port Port to write to
  * @param val Value to write
+ *
  */
 static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
-        asm volatile ("outl %0, %w1\n" : : "a" (val), "d" (port));
+        asm volatile (
+                "outl %[val], %w[port]\n"
+                :: [val] "a" (val), [port] "d" (port)
+        );
 }
 
@@ -141 +160 @@
  * @param port Port to read from
  * @return Value read
+ *
  */
 static inline uint8_t pio_read_8(ioport8_t *port)
@@ -146 +166 @@
         uint8_t val;
         
-        asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port));
+        asm volatile (
+                "inb %w[port], %b[val]\n"
+                : [val] "=a" (val)
+                : [port] "d" (port)
+        );
+        
         return val;
 }
@@ -156 +181 @@
  * @param port Port to read from
  * @return Value read
+ *
  */
 static inline uint16_t pio_read_16(ioport16_t *port)
@@ -161 +187 @@
         uint16_t val;
         
-        asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port));
+        asm volatile (
+                "inw %w[port], %w[val]\n"
+                : [val] "=a" (val)
+                : [port] "d" (port)
+        );
+        
         return val;
 }
@@ -171 +202 @@
  * @param port Port to read from
  * @return Value read
+ *
  */
 static inline uint32_t pio_read_32(ioport32_t *port)
@@ -176 +208 @@
         uint32_t val;
         
-        asm volatile ("inl %w1, %0 \n" : "=a" (val) : "d" (port));
+        asm volatile (
+                "inl %w[port], %[val]\n"
+                : [val] "=a" (val)
+                : [port] "d" (port)
+        );
+        
         return val;
 }
@@ -186 +223 @@
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_enable(void)
 {
         ipl_t v;
-        asm volatile (
-                "pushf\n\t"
-                "popl %0\n\t"
+        
+        asm volatile (
+                "pushf\n"
+                "popl %[v]\n"
                 "sti\n"
-                : "=r" (v)
-        );
+                : [v] "=r" (v)
+        );
+        
         return v;
 }
@@ -205 +245 @@
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_disable(void)
 {
         ipl_t v;
-        asm volatile (
-                "pushf\n\t"
-                "popl %0\n\t"
+        
+        asm volatile (
+                "pushf\n"
+                "popl %[v]\n"
                 "cli\n"
-                : "=r" (v)
-        );
+                : [v] "=r" (v)
+        );
+        
         return v;
 }
@@ -223 +266 @@
  *
  * @param ipl Saved interrupt priority level.
+ *
  */
 static inline void interrupts_restore(ipl_t ipl)
 {
         asm volatile (
-                "pushl %0\n\t"
+                "pushl %[ipl]\n"
                 "popf\n"
-                : : "r" (ipl)
+                :: [ipl] "r" (ipl)
         );
 }
@@ -236 +280 @@
  *
  * @return EFLAFS.
+ *
  */
 static inline ipl_t interrupts_read(void)
 {
         ipl_t v;
-        asm volatile (
-                "pushf\n\t"
-                "popl %0\n"
-                : "=r" (v)
-        );
+        
+        asm volatile (
+                "pushf\n"
+                "popl %[v]\n"
+                : [v] "=r" (v)
+        );
+        
         return v;
 }
@@ -251 +298 @@
 static inline void write_msr(uint32_t msr, uint64_t value)
 {
-        asm volatile ("wrmsr" : : "c" (msr), "a" ((uint32_t)(value)),
-            "d" ((uint32_t)(value >> 32)));
+        asm volatile (
+                "wrmsr"
+                :: "c" (msr), "a" ((uint32_t) (value)),
+                   "d" ((uint32_t) (value >> 32))
+        );
 }
 
@@ -258 +308 @@
 {
         uint32_t ax, dx;
-
-        asm volatile ("rdmsr" : "=a"(ax), "=d"(dx) : "c" (msr));
-        return ((uint64_t)dx << 32) | ax;
+        
+        asm volatile (
+                "rdmsr"
+                : "=a" (ax), "=d" (dx)
+                : "c" (msr)
+        );
+        
+        return ((uint64_t) dx << 32) | ax;
 }
 
@@ -269 +324 @@
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
@@ -275 +331 @@
         
         asm volatile (
-                "andl %%esp, %0\n"
-                : "=r" (v)
+                "andl %%esp, %[v]\n"
+                : [v] "=r" (v)
                 : "0" (~(STACK_SIZE - 1))
         );
@@ -287 +343 @@
 {
         uintptr_t *ip;
-
-        asm volatile (
-                "mov %%eip, %0"
-                : "=r" (ip)
-                );
+        
+        asm volatile (
+                "mov %%eip, %[ip]"
+                : [ip] "=r" (ip)
+        );
+        
         return ip;
 }
@@ -298 +355 @@
  *
  * @param addr Address on a page whose TLB entry is to be invalidated.
+ *
  */
 static inline void invlpg(uintptr_t addr)
 {
-        asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
+        asm volatile (
+                "invlpg %[addr]\n"
+                :: [addr] "m" (*(unative_t *) addr)
+        );
 }
 
@@ -307 +368 @@
  *
  * @param gdtr_reg Address of memory from where to load GDTR.
+ *
  */
 static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
-        asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
+        asm volatile (
+                "lgdtl %[gdtr_reg]\n"
+                :: [gdtr_reg] "m" (*gdtr_reg)
+        );
 }
 
@@ -316 +381 @@
  *
  * @param gdtr_reg Address of memory to where to load GDTR.
+ *
  */
 static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
-        asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
+        asm volatile (
+                "sgdtl %[gdtr_reg]\n"
+                :: [gdtr_reg] "m" (*gdtr_reg)
+        );
 }
 
@@ -325 +394 @@
  *
  * @param idtr_reg Address of memory from where to load IDTR.
+ *
  */
 static inline void idtr_load(ptr_16_32_t *idtr_reg)
 {
-        asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
+        asm volatile (
+                "lidtl %[idtr_reg]\n" 
+                :: [idtr_reg] "m" (*idtr_reg)
+        );
 }
 
@@ -334 +407 @@
  *
  * @param sel Selector specifying descriptor of TSS segment.
+ *
  */
 static inline void tr_load(uint16_t sel)
 {
-        asm volatile ("ltr %0" : : "r" (sel));
+        asm volatile (
+                "ltr %[sel]"
+                :: [sel] "r" (sel)
+        );
 }