Changeset aa85487 in mainline for kernel/arch/ia32/include/atomic.h


Ignore:
Timestamp:
2010-03-07T15:11:56Z (14 years ago)
Author:
Lukas Mejdrech <lukasmejdrech@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
aadf01e
Parents:
2e99277 (diff), 137691a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes, revision 308

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/include/atomic.h

    r2e99277 raa85487  
    4040#include <preemption.h>
    4141
    42 static inline void atomic_inc(atomic_t *val) {
     42static inline void atomic_inc(atomic_t *val)
     43{
    4344#ifdef CONFIG_SMP
    4445        asm volatile (
     
    5455}
    5556
    56 static inline void atomic_dec(atomic_t *val) {
     57static inline void atomic_dec(atomic_t *val)
     58{
    5759#ifdef CONFIG_SMP
    5860        asm volatile (
     
    6870}
    6971
    70 static inline long atomic_postinc(atomic_t *val)
     72static inline atomic_count_t atomic_postinc(atomic_t *val)
    7173{
    72         long r = 1;
     74        atomic_count_t r = 1;
    7375       
    7476        asm volatile (
    7577                "lock xaddl %[r], %[count]\n"
    76                 : [count] "+m" (val->count), [r] "+r" (r)
     78                : [count] "+m" (val->count),
     79                  [r] "+r" (r)
    7780        );
    7881       
     
    8083}
    8184
    82 static inline long atomic_postdec(atomic_t *val)
     85static inline atomic_count_t atomic_postdec(atomic_t *val)
    8386{
    84         long r = -1;
     87        atomic_count_t r = -1;
    8588       
    8689        asm volatile (
    8790                "lock xaddl %[r], %[count]\n"
    88                 : [count] "+m" (val->count), [r] "+r"(r)
     91                : [count] "+m" (val->count),
     92                  [r] "+r" (r)
    8993        );
    9094       
     
    9599#define atomic_predec(val)  (atomic_postdec(val) - 1)
    96100
    97 static inline uint32_t test_and_set(atomic_t *val) {
    98         uint32_t v;
     101static inline atomic_count_t test_and_set(atomic_t *val)
     102{
     103        atomic_count_t v = 1;
    99104       
    100105        asm volatile (
    101                 "movl $1, %[v]\n"
    102106                "xchgl %[v], %[count]\n"
    103                 : [v] "=r" (v), [count] "+m" (val->count)
     107                : [v] "+r" (v),
     108                  [count] "+m" (val->count)
    104109        );
    105110       
     
    110115static inline void atomic_lock_arch(atomic_t *val)
    111116{
    112         uint32_t tmp;
     117        atomic_count_t tmp;
    113118       
    114119        preemption_disable();
     
    124129                "testl %[tmp], %[tmp]\n"
    125130                "jnz 0b\n"
    126                 : [count] "+m" (val->count), [tmp] "=&r" (tmp)
     131                : [count] "+m" (val->count),
     132                  [tmp] "=&r" (tmp)
    127133        );
     134       
    128135        /*
    129136         * Prevent critical section code from bleeding out this way up.
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