Changeset a1b9f63 in mainline


Ignore:
Timestamp:
2018-08-31T10:32:40Z (6 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6bf5b8c
Parents:
b1834a01
git-author:
Jakub Jermar <jakub@…> (2018-08-31 09:54:11)
git-committer:
Jakub Jermar <jakub@…> (2018-08-31 10:32:40)
Message:

Add alignment argument to km_map()

km_map() currently always applies alignment requirement equal to the
size of the mapped region. Most of the time, the natural alignment is
unnecessarily strong and especially on 32-bit systems may contribute to
km_map() failures for regions with size in the order of several hundred
megabytes.

This change adds an extra argument to km_map() which allows the caller
to indicate the desired alignment. The old behaviour can be specified
by passing KM_NATURAL_ALIGNMENT as alignment.

This change only adds the alignment argument, but does not change the
alignment requirement anywhere.

Location:
kernel
Files:
29 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/src/vreg.c

    rb1834a01 ra1b9f63  
    6666                panic("Cannot allocate VREG frame.");
    6767
    68         page = (uint64_t *) km_map(frame, PAGE_SIZE,
     68        page = (uint64_t *) km_map(frame, PAGE_SIZE, PAGE_SIZE,
    6969            PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
    7070

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    rb1834a01 ra1b9f63  
    102102        beagleboard.irc_addr =
    103103            (void *) km_map(AMDM37x_IRC_BASE_ADDRESS, AMDM37x_IRC_SIZE,
    104             PAGE_NOT_CACHEABLE);
     104            KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    105105        assert(beagleboard.irc_addr);
    106106        omap_irc_init(beagleboard.irc_addr);

  • kernel/arch/arm32/src/mach/beaglebone/beaglebone.c

    rb1834a01 ra1b9f63  
    8888{
    8989        bbone.irc_addr = (void *) km_map(AM335x_IRC_BASE_ADDRESS,
    90             AM335x_IRC_SIZE, PAGE_NOT_CACHEABLE);
     90            AM335x_IRC_SIZE, KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    9191
    9292        bbone.cm_per_addr = (void *) km_map(AM335x_CM_PER_BASE_ADDRESS,
    93             AM335x_CM_PER_SIZE, PAGE_NOT_CACHEABLE);
     93            AM335x_CM_PER_SIZE, KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    9494
    9595        bbone.cm_dpll_addr = (void *) km_map(AM335x_CM_DPLL_BASE_ADDRESS,
    96             AM335x_CM_DPLL_SIZE, PAGE_NOT_CACHEABLE);
     96            AM335x_CM_DPLL_SIZE, KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    9797
    9898        bbone.ctrl_module = (void *) km_map(AM335x_CTRL_MODULE_BASE_ADDRESS,
    99             AM335x_CTRL_MODULE_SIZE, PAGE_NOT_CACHEABLE);
     99            AM335x_CTRL_MODULE_SIZE, KM_NATURAL_ALIGNMENT,
     100            PAGE_NOT_CACHEABLE);
    100101
    101102        assert(bbone.irc_addr != NULL);

  • kernel/arch/arm32/src/mach/gta02/gta02.c

    rb1834a01 ra1b9f63  
    103103
    104104        gta02_timer = (void *) km_map(S3C24XX_TIMER_ADDRESS, PAGE_SIZE,
    105             PAGE_NOT_CACHEABLE);
    106         irqc_regs = (void *) km_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE,
     105            PAGE_SIZE, PAGE_NOT_CACHEABLE);
     106        irqc_regs = (void *) km_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE, PAGE_SIZE,
    107107            PAGE_NOT_CACHEABLE);
    108108

  • kernel/arch/arm32/src/mach/integratorcp/integratorcp.c

    rb1834a01 ra1b9f63  
    135135void icp_init(void)
    136136{
    137         icp.hw_map.uart = km_map(ICP_UART, PAGE_SIZE,
    138             PAGE_WRITE | PAGE_NOT_CACHEABLE);
    139         icp.hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_NOT_CACHEABLE);
     137        icp.hw_map.uart = km_map(ICP_UART, PAGE_SIZE, PAGE_SIZE,
     138            PAGE_WRITE | PAGE_NOT_CACHEABLE);
     139        icp.hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_SIZE,
     140            PAGE_NOT_CACHEABLE);
    140141        icp.hw_map.kbd_stat = icp.hw_map.kbd_ctrl + ICP_KBD_STAT;
    141142        icp.hw_map.kbd_data = icp.hw_map.kbd_ctrl + ICP_KBD_DATA;
    142143        icp.hw_map.kbd_intstat = icp.hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
    143         icp.hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE,
     144        icp.hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE, PAGE_SIZE,
    144145            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    145146        icp.hw_map.rtc1_load = icp.hw_map.rtc + ICP_RTC1_LOAD_OFFSET;
    … …  
    150151        icp.hw_map.rtc1_intrstat = icp.hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;
    151152
    152         icp.hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE,
     153        icp.hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE, PAGE_SIZE,
    153154            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    154155        icp.hw_map.irqc_mask = icp.hw_map.irqc + ICP_IRQC_MASK_OFFSET;
    155156        icp.hw_map.irqc_unmask = icp.hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;
    156         icp.hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE,
     157        icp.hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE, PAGE_SIZE,
    157158            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    158159        icp.hw_map.sdramcr = icp.hw_map.cmcr + ICP_SDRAMCR_OFFSET;
    159         icp.hw_map.vga = km_map(ICP_VGA, PAGE_SIZE,
     160        icp.hw_map.vga = km_map(ICP_VGA, PAGE_SIZE, PAGE_SIZE,
    160161            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    161162

  • kernel/arch/arm32/src/mach/raspberrypi/raspberrypi.c

    rb1834a01 ra1b9f63  
    103103        /* Initialize interrupt controller */
    104104        raspi.irc = (void *) km_map(BCM2835_IRC_ADDR, sizeof(bcm2835_irc_t),
    105             PAGE_NOT_CACHEABLE);
     105            KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    106106        assert(raspi.irc);
    107107        bcm2835_irc_init(raspi.irc);
    … …  
    109109        /* Initialize system timer */
    110110        raspi.timer = (void *) km_map(BCM2835_TIMER_ADDR,
    111             sizeof(bcm2835_timer_t),
    112             PAGE_NOT_CACHEABLE);
     111            sizeof(bcm2835_timer_t), KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    113112}
    114113

  • kernel/arch/arm32/src/ras.c

    rb1834a01 ra1b9f63  
    5656                frame = frame_alloc(1, FRAME_LOWMEM, 0);
    5757
    58         ras_page = (uintptr_t *) km_map(frame,
    59             PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
     58        ras_page = (uintptr_t *) km_map(frame, PAGE_SIZE, PAGE_SIZE,
     59            PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
    6060
    6161        memsetb(ras_page, PAGE_SIZE, 0);

  • kernel/arch/ia32/src/smp/smp.c

    rb1834a01 ra1b9f63  
    7676        if (config.cpu_count > 1) {
    7777                l_apic = (uint32_t *) km_map((uintptr_t) l_apic, PAGE_SIZE,
    78                     PAGE_WRITE | PAGE_NOT_CACHEABLE);
     78                    PAGE_SIZE, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    7979                io_apic = (uint32_t *) km_map((uintptr_t) io_apic, PAGE_SIZE,
    80                     PAGE_WRITE | PAGE_NOT_CACHEABLE);
     80                    PAGE_SIZE, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    8181        }
    8282}

  • kernel/arch/ia32/src/vreg.c

    rb1834a01 ra1b9f63  
    6767                panic("Cannot allocate VREG frame.");
    6868
    69         page = (uint32_t *) km_map(frame, PAGE_SIZE,
     69        page = (uint32_t *) km_map(frame, PAGE_SIZE, PAGE_SIZE,
    7070            PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
    7171

  • kernel/arch/ia64/src/ia64.c

    rb1834a01 ra1b9f63  
    106106static void iosapic_init(void)
    107107{
    108         uintptr_t IOSAPIC = km_map(iosapic_base, PAGE_SIZE,
     108        uintptr_t IOSAPIC = km_map(iosapic_base, PAGE_SIZE, PAGE_SIZE,
    109109            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    110110        int i;
    … …  
    136136                /* Map the page with legacy I/O. */
    137137                legacyio_virt_base = km_map(LEGACYIO_PHYS_BASE, LEGACYIO_SIZE,
    138                     PAGE_WRITE | PAGE_NOT_CACHEABLE);
     138                    KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    139139
    140140                iosapic_init();

  • kernel/arch/ppc32/src/drivers/pic.c

    rb1834a01 ra1b9f63  
    4242void pic_init(uintptr_t base, size_t size, cir_t *cir, void **cir_arg)
    4343{
    44         pic = (uint32_t *) km_map(base, size, PAGE_WRITE | PAGE_NOT_CACHEABLE);
     44        pic = (uint32_t *) km_map(base, size, KM_NATURAL_ALIGNMENT,
     45            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    4546        *cir = pic_ack_interrupt;
    4647        *cir_arg = NULL;

  • kernel/arch/ppc32/src/ppc32.c

    rb1834a01 ra1b9f63  
    242242
    243243                cuda_t *cuda = (cuda_t *) (km_map(aligned_addr, offset + size,
     244                    KM_NATURAL_ALIGNMENT,
    244245                    PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset);
    245246

  • kernel/arch/sparc64/src/drivers/kbd.c

    rb1834a01 ra1b9f63  
    119119
    120120        ioport8_t *ns16550 = (ioport8_t *) (km_map(aligned_addr, offset + size,
    121             PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset);
     121            KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset);
    122122
    123123        ns16550_instance_t *ns16550_instance = ns16550_init(ns16550, 0, inr, cir,

  • kernel/arch/sparc64/src/drivers/pci.c

    rb1834a01 ra1b9f63  
    110110        pci->op = &pci_sabre_ops;
    111111        pci->reg = (uint64_t *) km_map(paddr, reg[SABRE_INTERNAL_REG].size,
    112             PAGE_WRITE | PAGE_NOT_CACHEABLE);
     112            KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    113113
    114114        return pci;
    … …  
    152152        pci->op = &pci_psycho_ops;
    153153        pci->reg = (uint64_t *) km_map(paddr, reg[PSYCHO_INTERNAL_REG].size,
    154             PAGE_WRITE | PAGE_NOT_CACHEABLE);
     154            KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    155155
    156156        return pci;

  • kernel/genarch/include/genarch/drivers/amdm37x/gpt.h

    rb1834a01 ra1b9f63  
    208208        // TODO find a nicer way to setup 32kHz clock source for timer1
    209209        // reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
    210         ioport32_t *clksel = (void *) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
     210        ioport32_t *clksel = (void *) km_map(0x48004C40, 4, PAGE_SIZE,
     211            PAGE_NOT_CACHEABLE);
    211212        *clksel &= ~1;
    212213        km_unmap((uintptr_t)clksel, 4);
    … …  
    214215        assert(timer);
    215216        /* Map control register */
    216         timer->regs = (void *) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
     217        timer->regs = (void *) km_map(ioregs, iosize, KM_NATURAL_ALIGNMENT,
     218            PAGE_NOT_CACHEABLE);
    217219
    218220        /* Reset the timer */

  • kernel/genarch/src/acpi/acpi.c

    rb1834a01 ra1b9f63  
    105105        /* Start with mapping the header only. */
    106106        vhdr = (struct acpi_sdt_header *) km_map((uintptr_t) psdt,
    107             sizeof(struct acpi_sdt_header), PAGE_READ | PAGE_NOT_CACHEABLE);
     107            sizeof(struct acpi_sdt_header), KM_NATURAL_ALIGNMENT,
     108            PAGE_READ | PAGE_NOT_CACHEABLE);
    108109
    109110        /* Now we can map the entire structure. */
    110111        vsdt = (struct acpi_sdt_header *) km_map((uintptr_t) psdt,
    111             vhdr->length, PAGE_WRITE | PAGE_NOT_CACHEABLE);
     112            vhdr->length, KM_NATURAL_ALIGNMENT,
     113            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    112114
    113115        // TODO: do not leak vtmp

  • kernel/genarch/src/drivers/am335x/timer.c

    rb1834a01 ra1b9f63  
    101101        size = regs_map[id].size;
    102102
    103         timer->regs = (void *) km_map(base_addr, size, PAGE_NOT_CACHEABLE);
     103        timer->regs = (void *) km_map(base_addr, size, KM_NATURAL_ALIGNMENT,
     104            PAGE_NOT_CACHEABLE);
    104105        assert(timer->regs != NULL);
    105106

  • kernel/genarch/src/drivers/bcm2835/mbox.c

    rb1834a01 ra1b9f63  
    9393
    9494        fb_mbox = (void *) km_map(BCM2835_MBOX0_ADDR, sizeof(bcm2835_mbox_t),
    95             PAGE_NOT_CACHEABLE);
     95            KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    9696
    9797        fb_desc->width = 640;

  • kernel/genarch/src/drivers/ega/ega.c

    rb1834a01 ra1b9f63  
    601601        instance->base = base;
    602602        instance->addr = (uint8_t *) km_map(addr, EGA_VRAM_SIZE,
    603             PAGE_WRITE | PAGE_NOT_CACHEABLE);
     603            KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    604604        if (!instance->addr) {
    605605                LOG("Unable to EGA video memory.");

  • kernel/genarch/src/drivers/omap/uart.c

    rb1834a01 ra1b9f63  
    8888{
    8989        assert(uart);
    90         uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
     90        uart->regs = (void *)km_map(addr, size, KM_NATURAL_ALIGNMENT,
     91            PAGE_NOT_CACHEABLE);
    9192
    9293        assert(uart->regs);

  • kernel/genarch/src/drivers/pl011/pl011.c

    rb1834a01 ra1b9f63  
    100100        assert(uart);
    101101        uart->regs = (void *)km_map(addr, sizeof(pl011_uart_regs_t),
    102             PAGE_NOT_CACHEABLE);
     102            KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
    103103        assert(uart->regs);
    104104

  • kernel/genarch/src/drivers/s3c24xx/uart.c

    rb1834a01 ra1b9f63  
    116116        uart_dev->data = uart;
    117117
    118         uart->io = (s3c24xx_uart_io_t *) km_map(paddr, PAGE_SIZE,
     118        uart->io = (s3c24xx_uart_io_t *) km_map(paddr, PAGE_SIZE, PAGE_SIZE,
    119119            PAGE_WRITE | PAGE_NOT_CACHEABLE);
    120120        uart->indev = NULL;

  • kernel/genarch/src/fb/fb.c

    rb1834a01 ra1b9f63  
    610610
    611611        instance->addr = (uint8_t *) km_map((uintptr_t) props->addr, fbsize,
    612             PAGE_WRITE | PAGE_NOT_CACHEABLE);
     612            KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE);
    613613        if (!instance->addr) {
    614614                LOG("Unable to map framebuffer.");

  • kernel/generic/include/mm/km.h

    rb1834a01 ra1b9f63  
    3939#include <mm/frame.h>
    4040
     41#define KM_NATURAL_ALIGNMENT    -1U
     42
    4143extern void km_identity_init(void);
    4244extern void km_non_identity_init(void);
    … …  
    4951extern bool km_is_non_identity(uintptr_t);
    5052
    51 extern uintptr_t km_map(uintptr_t, size_t, unsigned int);
     53extern uintptr_t km_map(uintptr_t, size_t, size_t, unsigned int);
    5254extern void km_unmap(uintptr_t, size_t);
    5355

  • kernel/generic/src/console/cmd.c

    rb1834a01 ra1b9f63  
    728728#endif
    729729                ptr = (uint8_t *) km_map(argv[0].intval, sizeof(uint8_t),
    730                     PAGE_NOT_CACHEABLE);
     730                    PAGE_SIZE, PAGE_NOT_CACHEABLE);
    731731
    732732        const uint8_t val = pio_read_8(ptr);
    … …  
    758758#endif
    759759                ptr = (uint16_t *) km_map(argv[0].intval, sizeof(uint16_t),
    760                     PAGE_NOT_CACHEABLE);
     760                    PAGE_SIZE, PAGE_NOT_CACHEABLE);
    761761
    762762        const uint16_t val = pio_read_16(ptr);
    … …  
    788788#endif
    789789                ptr = (uint32_t *) km_map(argv[0].intval, sizeof(uint32_t),
    790                     PAGE_NOT_CACHEABLE);
     790                    PAGE_SIZE, PAGE_NOT_CACHEABLE);
    791791
    792792        const uint32_t val = pio_read_32(ptr);
    … …  
    818818#endif
    819819                ptr = (uint8_t *) km_map(argv[0].intval, sizeof(uint8_t),
    820                     PAGE_NOT_CACHEABLE);
     820                    PAGE_SIZE, PAGE_NOT_CACHEABLE);
    821821
    822822        printf("write %" PRIxn ": %" PRIx8 "\n", argv[0].intval,
    … …  
    849849#endif
    850850                ptr = (uint16_t *) km_map(argv[0].intval, sizeof(uint16_t),
    851                     PAGE_NOT_CACHEABLE);
     851                    PAGE_SIZE, PAGE_NOT_CACHEABLE);
    852852
    853853        printf("write %" PRIxn ": %" PRIx16 "\n", argv[0].intval,
    … …  
    880880#endif
    881881                ptr = (uint32_t *) km_map(argv[0].intval, sizeof(uint32_t),
    882                     PAGE_NOT_CACHEABLE);
     882                    PAGE_SIZE, PAGE_NOT_CACHEABLE);
    883883
    884884        printf("write %" PRIxn ": %" PRIx32 "\n", argv[0].intval,

  • kernel/generic/src/ipc/irq.c

    rb1834a01 ra1b9f63  
    9595#endif
    9696                ranges[i].base = km_map(pbase[i], ranges[i].size,
     97                    KM_NATURAL_ALIGNMENT,
    9798                    PAGE_READ | PAGE_WRITE | PAGE_KERNEL | PAGE_NOT_CACHEABLE);
    9899                if (!ranges[i].base) {

  • kernel/generic/src/main/kinit.c

    rb1834a01 ra1b9f63  
    249249                 */
    250250                uintptr_t page = km_map(init.tasks[i].paddr,
    251                     init.tasks[i].size,
     251                    init.tasks[i].size, KM_NATURAL_ALIGNMENT,
    252252                    PAGE_READ | PAGE_WRITE | PAGE_CACHEABLE);
    253253                assert(page);

  • kernel/generic/src/mm/km.c

    rb1834a01 ra1b9f63  
    130130
    131131static uintptr_t
    132 km_map_aligned(uintptr_t paddr, size_t size, unsigned int flags)
     132km_map_aligned(uintptr_t paddr, size_t size, size_t align, unsigned int flags)
    133133{
    134134        uintptr_t vaddr;
    135         size_t align;
    136135        uintptr_t offs;
     136
     137        if (align == KM_NATURAL_ALIGNMENT)
     138                align = ispwr2(size) ? size : (1U << (fnzb(size) + 1));
    137139
    138140        assert(ALIGN_DOWN(paddr, FRAME_SIZE) == paddr);
    139141        assert(ALIGN_UP(size, FRAME_SIZE) == size);
    140 
    141         /* Enforce natural or at least PAGE_SIZE alignment. */
    142         align = ispwr2(size) ? size : (1U << (fnzb(size) + 1));
     142        assert(ispwr2(align));
     143
     144        /* Enforce at least PAGE_SIZE alignment. */
    143145        vaddr = km_page_alloc(size, max(PAGE_SIZE, align));
    144146
    … …  
    185187 * @return New virtual address mapped to paddr.
    186188 */
    187 uintptr_t km_map(uintptr_t paddr, size_t size, unsigned int flags)
     189uintptr_t km_map(uintptr_t paddr, size_t size, size_t align, unsigned int flags)
    188190{
    189191        uintptr_t page;
    … …  
    192194        offs = paddr - ALIGN_DOWN(paddr, FRAME_SIZE);
    193195        page = km_map_aligned(ALIGN_DOWN(paddr, FRAME_SIZE),
    194             ALIGN_UP(size + offs, FRAME_SIZE), flags);
     196            ALIGN_UP(size + offs, FRAME_SIZE), align, flags);
    195197
    196198        return page + offs;
    … …  
    256258        frame = frame_alloc(1, FRAME_HIGHMEM | FRAME_ATOMIC | flags, 0);
    257259        if (frame) {
    258                 page = km_map(frame, PAGE_SIZE,
     260                page = km_map(frame, PAGE_SIZE, PAGE_SIZE,
    259261                    PAGE_READ | PAGE_WRITE | PAGE_CACHEABLE);
    260262                if (!page) {

  • kernel/test/mm/mapping1.c

    rb1834a01 ra1b9f63  
    4343        uintptr_t frame = frame_alloc(1, FRAME_NONE, 0);
    4444
    45         uintptr_t page0 = km_map(frame, FRAME_SIZE,
     45        uintptr_t page0 = km_map(frame, FRAME_SIZE, FRAME_SIZE,
    4646            PAGE_READ | PAGE_WRITE | PAGE_CACHEABLE);
    4747        TPRINTF("Virtual address %p mapped to physical address %p.\n",
    4848            (void *) page0, (void *) frame);
    4949
    50         uintptr_t page1 = km_map(frame, FRAME_SIZE,
     50        uintptr_t page1 = km_map(frame, FRAME_SIZE, FRAME_SIZE,
    5151            PAGE_READ | PAGE_WRITE | PAGE_CACHEABLE);
    5252        TPRINTF("Virtual address %p mapped to physical address %p.\n",
Note: See TracChangeset for help on using the changeset viewer.