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Changeset a0d1d9d in mainline


Ignore:
Timestamp:
2011-11-14T10:12:53Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
master
Children:
a066c1b9
Parents:
ec388d7
Message:

libc,hw_res: Add doxygen comment, make functions more robust.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/lib/c/generic/device/hw_res.c

    rec388d7 ra0d1d9d  
    4242{
    4343        sysarg_t count = 0;
    44        
     44
    4545        async_exch_t *exch = async_exchange_begin(sess);
     46        if (exch == NULL)
     47                return ENOMEM;
    4648        int rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    4749            HW_RES_GET_RESOURCE_LIST, &count);
    48        
     50
    4951        if (rc != EOK) {
    5052                async_exchange_end(exch);
    5153                return rc;
    5254        }
    53        
     55
    5456        size_t size = count * sizeof(hw_resource_t);
    5557        hw_resource_t *resources = (hw_resource_t *) malloc(size);
     
    5961                return ENOMEM;
    6062        }
    61        
     63
    6264        rc = async_data_read_start(exch, resources, size);
    6365        async_exchange_end(exch);
    64        
     66
    6567        if (rc != EOK) {
    6668                free(resources);
    6769                return rc;
    6870        }
    69        
     71
    7072        hw_resources->resources = resources;
    7173        hw_resources->count = count;
    72        
     74
    7375        return EOK;
    7476}
     
    7779{
    7880        async_exch_t *exch = async_exchange_begin(sess);
     81        if (exch == NULL)
     82                return false;
    7983        int rc = async_req_1_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    8084            HW_RES_ENABLE_INTERRUPT);
    8185        async_exchange_end(exch);
    82        
     86
    8387        return (rc == EOK);
    8488}
    8589
     90/**
     91 * Setup DMA channel to specified place and mode.
     92 * @param channel DMA Channel 1,2,3 for 8 bit transfers, 5,6,7 for 16 bit.
     93 * @param pa Physical address of the buffer. Must be < 16MB for 16 bit and < 1MB
     94 *           for 8 bit transfers.
     95 * @param size DMA buffer size, limited to 64K.
     96 * @param mode Mode of the DMA channel:
     97 *              - Read or Write
     98 *              - Allow automatic reset
     99 *              - Use address decrement instead of increment
     100 *              - Use SINGLE/BLOCK/ON DEMAND transfer mode
     101 * @return Error code.
     102 */
    86103int hw_res_dma_channel_setup(async_sess_t *sess,
    87104    unsigned channel, uint32_t pa, uint16_t size, uint8_t mode)
     
    90107        if (exch == NULL)
    91108                return ENOMEM;
    92         uint32_t packed = size | (mode << 16);
    93         int ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     109        const uint32_t packed = size | (mode << 16);
     110        const int ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    94111            HW_RES_DMA_CHANNEL_SETUP, channel, pa, packed);
    95112        async_exchange_end(exch);
    96        
     113
    97114        return ret;
    98115}
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