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Changeset a03b609 in mainline


Ignore:
Timestamp:
2013-01-19T18:17:27Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
26e3db2
Parents:
827aae5
Message:

arm32: Convert sctlr use to cp15 helpers.

Location:
kernel/arch/arm32
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/cp15.h

    r827aae5 ra03b609  
    149149
    150150/* System control registers */
     151/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
     152 * Manual ARMv7-A and ARMv7-R edition, page 1687 */
     153enum {
     154        SCTLR_MMU_EN_FLAG            = 1 << 0,
     155        SCTLR_ALIGN_CHECK_EN_FLAG    = 1 << 1,  /* Allow alignemnt check */
     156        SCTLR_CACHE_EN_FLAG          = 1 << 2,
     157        SCTLR_CP15_BARRIER_EN_FLAG   = 1 << 5,
     158        SCTLR_B_EN_FLAG              = 1 << 7,  /* ARMv6-, big endian switch */
     159        SCTLR_SWAP_EN_FLAG           = 1 << 10,
     160        SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11,
     161        SCTLR_INST_CACHE_EN_FLAG     = 1 << 12,
     162        SCTLR_HIGH_VECTORS_EN_FLAG   = 1 << 13,
     163        SCTLR_ROUND_ROBIN_EN_FLAG    = 1 << 14,
     164        SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17,
     165        SCTLR_WRITE_XN_EN_FLAG       = 1 << 19, /* Only if virt. supported */
     166        SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */
     167        SCTLR_FAST_IRQ_EN_FLAG       = 1 << 21, /* Disable impl. specific feat*/
     168        SCTLR_UNALIGNED_EN_FLAG      = 1 << 22, /* Must be 1 on armv7 */
     169        SCTLR_IRQ_VECTORS_EN_FLAG    = 1 << 24,
     170        SCTLR_BIG_ENDIAN_EXC_FLAG    = 1 << 25,
     171        SCTLR_NMFI_EN_FLAG           = 1 << 27,
     172        SCTLR_TEX_REMAP_EN_FLAG      = 1 << 28,
     173        SCTLR_ACCESS_FLAG_EN_FLAG    = 1 << 29,
     174        SCTLR_THUMB_EXC_EN_FLAG      = 1 << 30,
     175};
    151176CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0);
    152177CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
  • kernel/arch/arm32/include/regutils.h

    r827aae5 ra03b609  
    4040#define STATUS_REG_IRQ_DISABLED_BIT  (1 << 7)
    4141#define STATUS_REG_MODE_MASK         0x1f
    42 
    43 /* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
    44  * Manual ARMv7-A and ARMv7-R edition, page 1687 */
    45 #define CP15_R1_MMU_EN            (1 << 0)
    46 #define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
    47 #define CP15_R1_CACHE_EN          (1 << 2)
    48 #define CP15_R1_CP15_BARRIER_EN   (1 << 5)
    49 #define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only, big endian switch */
    50 #define CP15_R1_SWAP_EN           (1 << 10)
    51 #define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
    52 #define CP15_R1_INST_CACHE_EN     (1 << 12)
    53 #define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
    54 #define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
    55 #define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
    56 #define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
    57 #define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
    58 #define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
    59 #define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
    60 #define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
    61 #define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
    62 #define CP15_R1_NMFI_EN           (1 << 27)
    63 #define CP15_R1_TEX_REMAP_EN      (1 << 28)
    64 #define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
    65 #define CP15_R1_THUMB_EXC_EN      (1 << 30)
    6642
    6743/* ARM Processor Operation Modes */
  • kernel/arch/arm32/src/cpu/cpu.c

    r827aae5 ra03b609  
    129129void cpu_arch_init(void)
    130130{
    131         /* Get rid of any boot code hiding in ICache
    132          * This is safe without regards to ICache state. */
    133         memory_barrier();
    134         smc_coherence();
    135 
    136         uint32_t control_reg = 0;
    137         asm volatile (
    138                 "mrc p15, 0, %[control_reg], c1, c0"
    139                 : [control_reg] "=r" (control_reg)
    140         );
     131        uint32_t control_reg = SCTLR_read();
    141132       
    142133        /* Turn off tex remap, RAZ/WI prior to armv7 */
    143         control_reg &= ~CP15_R1_TEX_REMAP_EN;
     134        control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
    144135        /* Turn off accessed flag, RAZ/WI prior to armv7 */
    145         control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
     136        control_reg &= ~(SCTLR_ACCESS_FLAG_EN_FLAG | SCTLR_HW_ACCESS_FLAG_EN_FLAG);
    146137        /* Disable branch prediction RAZ/WI if not supported */
    147         control_reg &= ~CP15_R1_BRANCH_PREDICT_EN;
     138        control_reg &= ~SCTLR_BRANCH_PREDICT_EN_FLAG;
    148139
    149140        /* Unaligned access is supported on armv6+ */
     
    153144         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
    154145         * L.3.1 (p. 2456) */
    155         control_reg |= CP15_R1_UNALIGNED_EN;
     146        control_reg |= SCTLR_UNALIGNED_EN_FLAG;
    156147        /* Disable alignment checks, this turns unaligned access to undefined,
    157148         * unless U bit is set. */
    158         control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
     149        control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
    159150        /* Enable caching, On arm prior to armv7 there is only one level
    160151         * of caches. Data cache is coherent.
     
    167158         * L2 Cache for armv7 was enabled in boot code.
    168159         */
    169         control_reg |= CP15_R1_CACHE_EN;
     160        control_reg |= SCTLR_CACHE_EN_FLAG;
    170161#endif
    171162#ifdef PROCESSOR_cortex_a8
     
    173164          * Cortex-A8 implements IVIPT extension.
    174165          * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
    175         control_reg |= CP15_R1_INST_CACHE_EN;
    176 #endif
    177        
    178         asm volatile (
    179                 "mcr p15, 0, %[control_reg], c1, c0"
    180                 :: [control_reg] "r" (control_reg)
    181         );
     166        control_reg |= SCTLR_INST_CACHE_EN_FLAG;
     167#endif
     168        SCTLR_write(control_reg);
     169
    182170#ifdef CONFIG_FPU
    183171        fpu_setup();
  • kernel/arch/arm32/src/exception.c

    r827aae5 ra03b609  
    3939#include <interrupt.h>
    4040#include <arch/mm/page_fault.h>
     41#include <arch/cp15.h>
    4142#include <arch/barrier.h>
    4243#include <print.h>
     
    136137static void high_vectors(void)
    137138{
    138         uint32_t control_reg = 0;
    139         asm volatile (
    140                 "mrc p15, 0, %[control_reg], c1, c0"
    141                 : [control_reg] "=r" (control_reg)
    142         );
     139        uint32_t control_reg = SCTLR_read();
    143140       
    144141        /* switch on the high vectors bit */
    145         control_reg |= CP15_R1_HIGH_VECTORS_EN;
    146        
    147         asm volatile (
    148                 "mcr p15, 0, %[control_reg], c1, c0"
    149                 :: [control_reg] "r" (control_reg)
    150         );
     142        control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
     143       
     144        SCTLR_write(control_reg);
    151145}
    152146#endif
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