Changeset 9f351c8 in mainline


Ignore:
Timestamp:
2011-10-21T17:51:40Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7257eea6
Parents:
01aef43
Message:

sb16: DMA rework controller and channel initialization.

Location:
uspace/drv/audio/sb16
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/audio/sb16/dma_controller.c

    r01aef43 r9f351c8  
    148148        uint8_t *size_reg_address;
    149149        uint8_t *page_reg_address;
     150        uint8_t *single_mask_address;
     151        uint8_t *mode_address;
     152        uint8_t *flip_flop_address;
    150153} dma_channel_t;
    151154
     
    155158        dma_controller_regs_first_t *first;
    156159        dma_controller_regs_second_t *second;
     160        bool initialized;
    157161} dma_controller_t;
    158162
    159163static dma_controller_t controller_8237 = {
    160164        .channels = {
    161             { (uint8_t*)0x00, (uint8_t*)0x01, (uint8_t*)0x87 },
    162             { (uint8_t*)0x02, (uint8_t*)0x03, (uint8_t*)0x83 },
    163             { (uint8_t*)0x04, (uint8_t*)0x05, (uint8_t*)0x81 },
    164             { (uint8_t*)0x06, (uint8_t*)0x07, (uint8_t*)0x82 },
    165             { (uint8_t*)0xc0, (uint8_t*)0xc2, (uint8_t*)0x8f },
    166             { (uint8_t*)0xc4, (uint8_t*)0xc6, (uint8_t*)0x8b },
    167             { (uint8_t*)0xc8, (uint8_t*)0xca, (uint8_t*)0x89 },
    168             { (uint8_t*)0xcc, (uint8_t*)0xce, (uint8_t*)0x8a } },
     165            /* The first chip */
     166            { (uint8_t*)0x00, (uint8_t*)0x01, (uint8_t*)0x87,
     167              (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
     168            { (uint8_t*)0x02, (uint8_t*)0x03, (uint8_t*)0x83,
     169              (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
     170            { (uint8_t*)0x04, (uint8_t*)0x05, (uint8_t*)0x81,
     171              (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
     172            { (uint8_t*)0x06, (uint8_t*)0x07, (uint8_t*)0x82,
     173              (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
     174
     175            /* The second chip */
     176            { (uint8_t*)0xc0, (uint8_t*)0xc2, (uint8_t*)0x8f,
     177              (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
     178            { (uint8_t*)0xc4, (uint8_t*)0xc6, (uint8_t*)0x8b,
     179              (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
     180            { (uint8_t*)0xc8, (uint8_t*)0xca, (uint8_t*)0x89,
     181              (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
     182            { (uint8_t*)0xcc, (uint8_t*)0xce, (uint8_t*)0x8a,
     183              (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, }, },
     184
    169185        .page_table = NULL,
    170186        .first = NULL,
    171187        .second = NULL,
     188        .initialized = false,
    172189};
    173190
    174 static inline const dma_controller_t *dma_controller_init()
     191static inline int dma_controller_init(dma_controller_t *controller)
    175192{
     193        assert(controller);
    176194        int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
    177             (void**)&controller_8237.page_table);
     195            (void**)&controller->page_table);
    178196        if (ret != EOK)
    179                 return NULL;
     197                return EIO;
    180198
    181199        ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
    182200            sizeof(dma_controller_regs_first_t),
    183             (void**)&controller_8237.first);
     201            (void**)&controller->first);
    184202        if (ret != EOK)
    185                 return NULL;
     203                return EIO;
    186204
    187205        ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
    188206            sizeof(dma_controller_regs_second_t),
    189             (void**)&controller_8237.second);
     207            (void**)&controller->second);
    190208        if (ret != EOK)
    191                 return NULL;
    192         return &controller_8237;
    193 }
    194 /*----------------------------------------------------------------------------*/
    195 static int dma_setup_channel_8bit(const dma_controller_t *controller,
    196     unsigned channel, uint32_t pa, uint16_t size)
    197 {
    198         if (channel == 0 || channel > 3)
    199                 return ENOTSUP;
    200         assert(controller);
    201         /* Mask DMA request */
    202         uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
    203             | DMA_SINGLE_MASK_MASKED_FLAG;
    204         pio_write_8(&controller->first->single_mask, value);
    205 
    206         /* Set address -- reset flip-flop*/
    207         pio_write_8(&controller->first->flip_flop, 1);
    208 
    209         /* Low byte */
    210         value = pa & 0xff;
    211         pio_write_8(controller->channels[channel].offset_reg_address, value);
    212 
    213         /* High byte */
    214         value = (pa >> 8) & 0xff;
    215         pio_write_8(controller->channels[channel].offset_reg_address, value);
    216 
    217         /* Page address - third byte */
    218         value = (pa >> 16) & 0xff;
    219         pio_write_8(controller->channels[channel].offset_reg_address, value);
    220 
    221         /* Set size -- reset flip-flop */
    222         pio_write_8(&controller->first->flip_flop, 1);
    223 
    224         /* Low byte */
    225         value = size & 0xff;
    226         pio_write_8(controller->channels[channel].offset_reg_address, value);
    227 
    228         /* High byte */
    229         value = (size >> 8) & 0xff;
    230         pio_write_8(controller->channels[channel].offset_reg_address, value);
    231 
    232         /* Unmask DMA request */
    233         value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
    234         pio_write_8(&controller->first->single_mask, value);
    235 
    236         return EOK;
    237 }
    238 /*----------------------------------------------------------------------------*/
    239 static int dma_setup_channel_16bit(const dma_controller_t *controller,
    240     unsigned channel, uintptr_t pa, size_t size)
    241 {
    242         if (channel <= 4 || channel > 7)
    243                 return ENOTSUP;
    244         assert(controller);
    245         /* Mask DMA request */
    246         uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
    247             | DMA_SINGLE_MASK_MASKED_FLAG;
    248         pio_write_8(&controller->second->single_mask, value);
    249 
    250         /* Set address -- reset flip-flop*/
    251         pio_write_8(&controller->second->flip_flop, 1);
    252 
    253         /* Low byte */
    254         value = pa & 0xff;
    255         pio_write_8(controller->channels[channel].offset_reg_address, value);
    256 
    257         /* High byte */
    258         value = (pa >> 8) & 0xff;
    259         pio_write_8(controller->channels[channel].offset_reg_address, value);
    260 
    261         /* Page address - third byte */
    262         value = (pa >> 16) & 0xff;
    263         pio_write_8(controller->channels[channel].offset_reg_address, value);
    264 
    265         /* Set size -- reset flip-flop */
    266         pio_write_8(&controller->second->flip_flop, 1);
    267 
    268         /* Low byte */
    269         value = size & 0xff;
    270         pio_write_8(controller->channels[channel].offset_reg_address, value);
    271 
    272         /* High byte */
    273         value = (size >> 8) & 0xff;
    274         pio_write_8(controller->channels[channel].offset_reg_address, value);
    275 
    276         /* Unmask DMA request */
    277         value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
    278         pio_write_8(&controller->second->single_mask, value);
    279 
     209                return EIO;
     210        controller->initialized = true;
    280211        return EOK;
    281212}
     
    283214int dma_setup_channel(unsigned channel, uintptr_t pa, size_t size)
    284215{
    285         static const dma_controller_t *controller = NULL;
    286         if (!controller)
    287                 controller = dma_controller_init();
    288 
    289         if (!controller)
    290                 return EIO;
    291 
    292         if (channel < 4)
    293                 return dma_setup_channel_8bit(controller, channel, pa, size);
    294         else
    295                 return dma_setup_channel_16bit(controller, channel, pa, size);
     216        if (channel == 0 || channel == 4)
     217                return ENOTSUP;
     218
     219        if (channel > 7)
     220                return ENOENT;
     221
     222        if (!controller_8237.initialized)
     223                dma_controller_init(&controller_8237);
     224
     225        if (!controller_8237.initialized)
     226                return EIO;
     227
     228        dma_channel_t dma_channel = controller_8237.channels[channel];
     229
     230        /* Mask DMA request */
     231        uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
     232            | DMA_SINGLE_MASK_MASKED_FLAG;
     233        pio_write_8(dma_channel.single_mask_address, value);
     234
     235        /* Set address -- reset flip-flop*/
     236        pio_write_8(dma_channel.flip_flop_address, 1);
     237
     238        /* Low byte */
     239        value = pa & 0xff;
     240        pio_write_8(dma_channel.offset_reg_address, value);
     241
     242        /* High byte */
     243        value = (pa >> 8) & 0xff;
     244        pio_write_8(dma_channel.offset_reg_address, value);
     245
     246        /* Page address - third byte */
     247        value = (pa >> 16) & 0xff;
     248        pio_write_8(dma_channel.offset_reg_address, value);
     249
     250        /* Set size -- reset flip-flop */
     251        pio_write_8(dma_channel.flip_flop_address, 1);
     252
     253        /* Low byte */
     254        value = size & 0xff;
     255        pio_write_8(dma_channel.offset_reg_address, value);
     256
     257        /* High byte */
     258        value = (size >> 8) & 0xff;
     259        pio_write_8(dma_channel.offset_reg_address, value);
     260
     261        /* Unmask DMA request */
     262        value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
     263        pio_write_8(dma_channel.single_mask_address, value);
     264
     265        return EOK;
     266
     267}
     268/*----------------------------------------------------------------------------*/
     269int dma_prepare_channel(unsigned channel, bool write, transfer_mode_t mode)
     270{
     271        if (!controller_8237.initialized)
     272                return EIO;
     273
     274        return ENOTSUP;
    296275}
    297276/**
  • uspace/drv/audio/sb16/dma_controller.h

    r01aef43 r9f351c8  
    3535#define DRV_AUDIO_SB16_DMA_CONTROLLER_H
    3636
     37#include <bool.h>
     38
     39typedef enum {
     40        ON_DEMAND = 0x0,
     41        SINGLE_DMA = 0x1,
     42        BLOCK_DMA = 0x2,
     43} transfer_mode_t;
     44
    3745int dma_setup_channel(unsigned channel, uintptr_t pa, size_t size);
     46
     47int dma_prepare_channel(unsigned channel, bool write, transfer_mode_t mode);
    3848
    3949#endif
Note: See TracChangeset for help on using the changeset viewer.