Changeset 98a935e in mainline for kernel/genarch/include/genarch/drivers/ns16550/ns16550.h

Timestamp:

2021-08-04T19:30:39Z (3 years ago)

Author:

jxsvoboda <5887334+jxsvoboda@…>

Branches:

master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8bb0af7f, f05edcb

Parents:

31e15be

git-author:

Marek Benc <dusxmt@…> (2021-06-23 20:56:38)

git-committer:

jxsvoboda <5887334+jxsvoboda@…> (2021-08-04 19:30:39)

Message:

Configure NS16550 transmission format settings on initialization on PCs.

Currently, the NS116550 serial line controller is left with its
settings as it was left by the boot firmware and/or bootloader.
On my computer, this was an invalid configuration, and it left me
with a really slow booting system, since each output character
had to go through the full timeout loop in ns16550_sendb().

This patch adds the necessary bit and register descriptions to configure
the baud rate and transmission settings, as well as configuring them on
post-SMP initialization on ia32 and amd64, currently with values matching
the ns8250 userspace character device driver (38400 baud, 8-bit words,
2 stop bits, no parity).

This could perhaps be changed to be adjustable with a kernel command-line
argument, or through the configuration system.

This change does not affect emulators, since those largely ignore these
settings.

File:

• kernel/genarch/include/genarch/drivers/ns16550/ns16550.h (modified) (3 diffs)

kernel/genarch/include/genarch/drivers/ns16550/ns16550.h

@@ -43 +43 @@
 #include <console/chardev.h>
 
-#define IER_ERBFI  0x01  /** Enable Receive Buffer Full Interrupt. */
+#define NS156440_CLOCK    115200 /** Internal clock speed, max. baud rate. */
 
-#define LCR_DLAB   0x80  /** Divisor Latch Access bit. */
+#define IER_ERBFI         0x01   /** Enable Receive Buffer Full Interrupt. */
+#define MCR_OUT2          0x08   /** OUT2. */
 
-#define MCR_OUT2   0x08  /** OUT2. */
+#define LCR_DLAB          0x80   /** Divisor Latch Access bit. */
+#define LCR_SBE           0x40   /** RS-232 Break Signal bit. */
+
+#define LCR_PARITY_NONE   0x00   /** No parity bit. */
+#define LCR_PARITY_ODD    0x08   /** Odd parity. */
+#define LCR_PARITY_EVEN   0x18   /** Even parity. */
+#define LCR_PARITY_MARK   0x28   /** Parity bit always one. */
+#define LCR_PARITY_SPACE  0x38   /** Parity bit always zero. */
+
+#define LCR_STOP_BIT_ONE  0x00   /** One stop bit. */
+#define LCR_STOP_BIT_TWO  0x04   /** Two stop bits. */
+
+#define LCR_WORD_LEN_5    0x00   /** 5-bit word length. */
+#define LCR_WORD_LEN_6    0x01   /** 6-bit word length. */
+#define LCR_WORD_LEN_7    0x02   /** 7-bit word length. */
+#define LCR_WORD_LEN_8    0x03   /** 8-bit word length. */
 
 /** NS16550 registers. */
@@ -53 +69 @@
         NS16550_REG_RBR = 0,  /**< Receiver Buffer Register (read). */
         NS16550_REG_THR = 0,  /**< Transmitter Holder Register (write). */
+        NS16550_REG_DLL = 0,  /**< Baud rate divisor latch low byte (write). */
         NS16550_REG_IER = 1,  /**< Interrupt Enable Register. */
+        NS16550_REG_DLH = 1,  /**< Baud rate divisor latch high byte (write). */
         NS16550_REG_IIR = 2,  /**< Interrupt Ident Register (read). */
         NS16550_REG_FCR = 2,  /**< FIFO control register (write). */
@@ -73 +91 @@
 extern ns16550_instance_t *ns16550_init(ioport8_t *, unsigned, inr_t, cir_t,
     void *, outdev_t **);
+extern void ns16550_format_set(ns16550_instance_t *, unsigned, uint8_t);
 extern void ns16550_wire(ns16550_instance_t *, indev_t *);