Changeset 97c7682 in mainline for kernel/genarch/src/mm/page_pt.c

Timestamp:

2012-07-14T11:18:40Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

804d9b6

Parents:

0747468 (diff), f0348c8 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Text conflict in boot/arch/arm32/Makefile.inc:

Trivial conflict around ifeq condition.

Text conflict in kernel/arch/arm32/include/mm/page.h:

Added defines and set_pt_levelx_present function.
COnflict looked horrible because of the armv4/v7 split.

File:

• kernel/genarch/src/mm/page_pt.c (modified) (10 diffs)

kernel/genarch/src/mm/page_pt.c

@@ -43 +43 @@
 #include <arch/mm/page.h>
 #include <arch/mm/as.h>
+#include <arch/barrier.h>
 #include <typedefs.h>
 #include <arch/asm.h>
@@ -48 +49 @@
 #include <align.h>
 #include <macros.h>
+#include <bitops.h>
 
 static void pt_mapping_insert(as_t *, uintptr_t, uintptr_t, unsigned int);
@@ -85 +87 @@
                 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt));
                 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page),
-                    PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
+                    PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
                     PAGE_WRITE);
+                write_barrier();
+                SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page));
         }
         
@@ -97 +101 @@
                 SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt));
                 SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page),
-                    PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
+                    PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
                     PAGE_WRITE);
+                write_barrier();
+                SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));       
         }
         
@@ -109 +115 @@
                 SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt));
                 SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page),
-                    PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
+                    PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
                     PAGE_WRITE);
+                write_barrier();
+                SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page));
         }
         
@@ -116 +124 @@
         
         SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame);
-        SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags);
+        SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT);
+        write_barrier();
+        SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page));
 }
 
@@ -278 +288 @@
         if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT)
                 return NULL;
+
+        read_barrier();
         
         pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
         if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT)
                 return NULL;
+
+#if (PTL1_ENTRIES != 0)
+        read_barrier();
+#endif
         
         pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
         if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT)
                 return NULL;
+
+#if (PTL2_ENTRIES != 0)
+        read_barrier();
+#endif
         
         pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
         
         return &ptl3[PTL3_INDEX(page)];
+}
+
+/** Return the size of the region mapped by a single PTL0 entry.
+ *
+ * @return Size of the region mapped by a single PTL0 entry.
+ */
+static uintptr_t ptl0_step_get(void)
+{
+        size_t va_bits;
+
+        va_bits = fnzb(PTL0_ENTRIES) + fnzb(PTL1_ENTRIES) + fnzb(PTL2_ENTRIES) +
+            fnzb(PTL3_ENTRIES) + PAGE_WIDTH;
+
+        return 1UL << (va_bits - fnzb(PTL0_ENTRIES));
 }
 
@@ -309 +343 @@
 {
         uintptr_t ptl0 = PA2KA((uintptr_t) AS_KERNEL->genarch.page_table);
-        uintptr_t ptl0step = (((uintptr_t) -1) / PTL0_ENTRIES) + 1;
+        uintptr_t ptl0_step = ptl0_step_get();
         size_t order;
         uintptr_t addr;
@@ -321 +355 @@
 #endif
 
-        ASSERT(ispwr2(ptl0step));
         ASSERT(size > 0);
 
-        for (addr = ALIGN_DOWN(base, ptl0step); addr - 1 < base + size - 1;
-            addr += ptl0step) {
+        for (addr = ALIGN_DOWN(base, ptl0_step); addr - 1 < base + size - 1;
+            addr += ptl0_step) {
                 uintptr_t l1;
 
@@ -332 +365 @@
                 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(addr), KA2PA(l1));
                 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(addr),
-                    PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
-                    PAGE_WRITE);
+                    PAGE_PRESENT | PAGE_USER | PAGE_CACHEABLE |
+                    PAGE_EXEC | PAGE_WRITE | PAGE_READ);
         }
 }