Changeset 948911d in mainline for uspace/drv/nic/e1k/e1k.h


Ignore:
Timestamp:
2012-01-24T02:27:43Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
230385c
Parents:
8afeb04 (diff), 2df6f6fe (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/nic/e1k/e1k.h

    r8afeb04 r948911d  
    3939#include <stdint.h>
    4040
    41 /** Ethernet CRC size after packet received in rx_descriptor */
     41/** Ethernet CRC size after frame received in rx_descriptor */
    4242#define E1000_CRC_SIZE  4
    4343
     
    8282} e1000_tx_descriptor_t;
    8383
     84/** E1000 boards */
     85typedef enum {
     86        E1000_82540,
     87        E1000_82541,
     88        E1000_82541REV2,
     89        E1000_82545,
     90        E1000_82546,
     91        E1000_82547,
     92        E1000_82572,
     93        E1000_80003ES2
     94} e1000_board_t;
     95
     96typedef struct {
     97        uint32_t eerd_start;
     98        uint32_t eerd_done;
     99       
     100        uint32_t eerd_address_offset;
     101        uint32_t eerd_data_offset;
     102} e1000_info_t;
     103
    84104/** VLAN tag bits */
    85 enum e1000_vlantag {
     105typedef enum {
    86106        VLANTAG_CFI = (1 << 12),  /**< Canonical Form Indicator */
    87 };
     107} e1000_vlantag_t;
    88108
    89109/** Transmit descriptor COMMAND field bits */
    90 enum e1000_txdescriptor_command {
    91         TXDESCRIPTOR_COMMAND_VLE = (1 << 6),   /**< VLAN Packet Enable */
     110typedef enum {
     111        TXDESCRIPTOR_COMMAND_VLE = (1 << 6),   /**< VLAN frame Enable */
    92112        TXDESCRIPTOR_COMMAND_RS = (1 << 3),    /**< Report Status */
    93113        TXDESCRIPTOR_COMMAND_IFCS = (1 << 1),  /**< Insert FCS */
    94114        TXDESCRIPTOR_COMMAND_EOP = (1 << 0)    /**< End Of Packet */
    95 };
     115} e1000_txdescriptor_command_t;
    96116
    97117/** Transmit descriptor STATUS field bits */
    98 enum e1000_txdescriptor_status {
     118typedef enum {
    99119        TXDESCRIPTOR_STATUS_DD = (1 << 0)  /**< Descriptor Done */
    100 };
     120} e1000_txdescriptor_status_t;
    101121
    102122/** E1000 Registers */
    103 enum e1000_registers {
     123typedef enum {
    104124        E1000_CTRL = 0x0,      /**< Device Control Register */
    105125        E1000_STATUS = 0x8,    /**< Device Status Register */
     
    130150        E1000_IMS = 0xD0,      /**< Interrupt Mask Set/Read Register */
    131151        E1000_IMC = 0xD8       /**< Interrupt Mask Clear Register */
    132 };
    133 
    134 /** EEPROM Read Register fields */
    135 enum e1000_eerd {
    136         /** Start Read */
    137         EERD_START = (1 << 0),
    138         /** Read Done */
    139         EERD_DONE = (1 << 4),
    140         /** Read Done for 82541xx and 82547GI/EI */
    141         EERD_DONE_82541XX_82547GI_EI = (1 << 1),
    142         /** Read Address offset */
    143         EERD_ADDRESS_OFFSET = 8,
    144         /** Read Address offset for 82541xx and 82547GI/EI */
    145         EERD_ADDRESS_OFFSET_82541XX_82547GI_EI = 2,
    146         /** Read Data */
    147         EERD_DATA_OFFSET = 16
    148 };
     152} e1000_registers_t;
    149153
    150154/** Device Control Register fields */
    151 enum e1000_ctrl {
     155typedef enum {
    152156        CTRL_FD = (1 << 0),    /**< Full-Duplex */
    153157        CTRL_LRST = (1 << 3),  /**< Link Reset */
     
    176180        CTRL_VME = (1 << 30),      /**< VLAN Mode Enable */
    177181        CTRL_PHY_RST = (1 << 31)   /**< PHY Reset */
    178 };
     182} e1000_ctrl_t;
    179183
    180184/** Device Status Register fields */
    181 enum e1000_status {
     185typedef enum {
    182186        STATUS_FD = (1 << 0),  /**< Link Full Duplex configuration Indication */
    183187        STATUS_LU = (1 << 1),  /**< Link Up Indication */
     
    197201        /** Link speed setting 1000 Mb/s value variant B */
    198202        STATUS_SPEED_1000B = 3,
    199 };
     203} e1000_status_t;
    200204
    201205/** Transmit IPG Register fields
     
    204208 *
    205209 */
    206 enum e1000_tipg {
     210typedef enum {
    207211        TIPG_IPGT_SHIFT = 0,    /**< IPG Transmit Time shift */
    208212        TIPG_IPGR1_SHIFT = 10,  /**< IPG Receive Time 1 */
    209213        TIPG_IPGR2_SHIFT = 20   /**< IPG Receive Time 2 */
    210 };
     214} e1000_tipg_t;
    211215
    212216/** Transmit Control Register fields */
    213 enum e1000_tctl {
     217typedef enum {
    214218        TCTL_EN = (1 << 1),    /**< Transmit Enable */
    215219        TCTL_PSP =  (1 << 3),  /**< Pad Short Packets */
    216220        TCTL_CT_SHIFT = 4,     /**< Collision Threshold shift */
    217221        TCTL_COLD_SHIFT = 12   /**< Collision Distance shift */
    218 };
     222} e1000_tctl_t;
    219223
    220224/** ICR register fields */
    221 enum e1000_icr {
     225typedef enum {
    222226        ICR_TXDW = (1 << 0),  /**< Transmit Descriptor Written Back */
    223227        ICR_RXT0 = (1 << 7)   /**< Receiver Timer Interrupt */
    224 };
     228} e1000_icr_t;
    225229
    226230/** RAH register fields */
    227 enum e1000_rah {
     231typedef enum {
    228232        RAH_AV = (1 << 31)   /**< Address Valid */
    229 };
     233} e1000_rah_t;
    230234
    231235/** RCTL register fields */
    232 enum e1000_rctl {
     236typedef enum {
    233237        RCTL_EN = (1 << 1),    /**< Receiver Enable */
    234238        RCTL_SBP = (1 << 2),   /**< Store Bad Packets */
     
    237241        RCTL_BAM = (1 << 15),  /**< Broadcast Accept Mode */
    238242        RCTL_VFE = (1 << 18)   /**< VLAN Filter Enable */
    239 };
     243} e1000_rctl_t;
    240244
    241245#endif
Note: See TracChangeset for help on using the changeset viewer.