Index: kernel/arch/mips32/src/mm/tlb.c
===================================================================
--- kernel/arch/mips32/src/mm/tlb.c	(revision edebc15c65ded52ed661523a687334ecc04a7578)
+++ kernel/arch/mips32/src/mm/tlb.c	(revision 91befde0e355dc8990678215dc7248b441b4c610)
@@ -48,13 +48,12 @@
 #include <interrupt.h>
 
-static void tlb_refill_fail(istate_t *istate);
-static void tlb_invalid_fail(istate_t *istate);
-static void tlb_modified_fail(istate_t *istate);
-
-static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
-
-/** Initialize TLB
- *
- * Initialize TLB.
+static void tlb_refill_fail(istate_t *);
+static void tlb_invalid_fail(istate_t *);
+static void tlb_modified_fail(istate_t *);
+
+static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
+
+/** Initialize TLB.
+ *
  * Invalidate all entries and mark wired entries.
  */
@@ -82,9 +81,7 @@
 }
 
-/** Process TLB Refill Exception
- *
- * Process TLB Refill Exception.
- *
- * @param istate Interrupted register context.
+/** Process TLB Refill Exception.
+ *
+ * @param istate	Interrupted register context.
  */
 void tlb_refill(istate_t *istate)
@@ -129,5 +126,6 @@
 
 	tlb_prepare_entry_hi(&hi, asid, badvaddr);
-	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+	    pte->pfn);
 
 	/*
@@ -135,5 +133,5 @@
 	 */
 	cp0_entry_hi_write(hi.value);
-	if ((badvaddr/PAGE_SIZE) % 2 == 0) {
+	if ((badvaddr / PAGE_SIZE) % 2 == 0) {
 		cp0_entry_lo0_write(lo.value);
 		cp0_entry_lo1_write(0);
@@ -154,9 +152,7 @@
 }
 
-/** Process TLB Invalid Exception
- *
- * Process TLB Invalid Exception.
- *
- * @param istate Interrupted register context.
+/** Process TLB Invalid Exception.
+ *
+ * @param istate	Interrupted register context.
  */
 void tlb_invalid(istate_t *istate)
@@ -218,10 +214,11 @@
 	pte->a = 1;
 
-	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+	    pte->pfn);
 
 	/*
 	 * The entry is to be updated in TLB.
 	 */
-	if ((badvaddr/PAGE_SIZE) % 2 == 0)
+	if ((badvaddr / PAGE_SIZE) % 2 == 0)
 		cp0_entry_lo0_write(lo.value);
 	else
@@ -238,9 +235,7 @@
 }
 
-/** Process TLB Modified Exception
- *
- * Process TLB Modified Exception.
- *
- * @param istate Interrupted register context.
+/** Process TLB Modified Exception.
+ *
+ * @param istate	Interrupted register context.
  */
 void tlb_modified(istate_t *istate)
@@ -309,10 +304,11 @@
 	pte->d = 1;
 
-	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
+	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
+	    pte->pfn);
 
 	/*
 	 * The entry is to be updated in TLB.
 	 */
-	if ((badvaddr/PAGE_SIZE) % 2 == 0)
+	if ((badvaddr / PAGE_SIZE) % 2 == 0)
 		cp0_entry_lo0_write(lo.value);
 	else
@@ -341,6 +337,8 @@
 		sym2 = s;
 
-	fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());
-	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
+	fault_if_from_uspace(istate, "TLB Refill Exception on %p",
+	    cp0_badvaddr_read());
+	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(),
+	    istate->epc, symbol, sym2);
 }
 
@@ -353,6 +351,8 @@
 	if (s)
 		symbol = s;
-	fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());
-	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
+	fault_if_from_uspace(istate, "TLB Invalid Exception on %p",
+	    cp0_badvaddr_read());
+	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(),
+	    istate->epc, symbol);
 }
 
@@ -364,21 +364,25 @@
 	if (s)
 		symbol = s;
-	fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());
-	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
-}
-
-/** Try to find PTE for faulting address
- *
- * Try to find PTE for faulting address.
+	fault_if_from_uspace(istate, "TLB Modified Exception on %p",
+	    cp0_badvaddr_read());
+	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(),
+	    istate->epc, symbol);
+}
+
+/** Try to find PTE for faulting address.
+ *
  * The AS->lock must be held on entry to this function.
  *
- * @param badvaddr Faulting virtual address.
- * @param access Access mode that caused the fault.
- * @param istate Pointer to interrupted state.
- * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
- *
- * @return PTE on success, NULL otherwise.
- */
-pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
+ * @param badvaddr	Faulting virtual address.
+ * @param access	Access mode that caused the fault.
+ * @param istate	Pointer to interrupted state.
+ * @param pfrc		Pointer to variable where as_page_fault() return code
+ * 			will be stored.
+ *
+ * @return		PTE on success, NULL otherwise.
+ */
+pte_t *
+find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
+    int *pfrc)
 {
 	entry_hi_t hi;
@@ -442,5 +446,7 @@
 }
 
-void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
+void
+tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
+    uintptr_t pfn)
 {
 	lo->value = 0;
@@ -481,8 +487,8 @@
 		
 		printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
-			i, hi.asid, hi.vpn2, mask.mask,
-			lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
+		    i, hi.asid, hi.vpn2, mask.mask,
+		    lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
 		printf("                    %1u %1u %1u %1u %#6x\n",
-			lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
+		    lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
 	}
 	
@@ -561,9 +567,10 @@
 }
 
-/** Invalidate TLB entries for specified page range belonging to specified address space.
- *
- * @param asid Address space identifier.
- * @param page First page whose TLB entry is to be invalidated.
- * @param cnt Number of entries to invalidate.
+/** Invalidate TLB entries for specified page range belonging to specified
+ * address space.
+ *
+ * @param asid		Address space identifier.
+ * @param page		First page whose TLB entry is to be invalidated.
+ * @param cnt		Number of entries to invalidate.
  */
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
@@ -589,5 +596,8 @@
 
 		if (!index.p) {
-			/* Entry was found, index register contains valid index. */
+			/*
+			 * Entry was found, index register contains valid
+			 * index.
+			 */
 			tlbr();
 
